Materials Science Forum Vol. 1062

Abstract: In this work, an AlGaN/GaN HEMT structure is grown on a 0.8 μm thick 3C-SiC layer on high resistivity Silicon substrate. The RF propagation losses are investigated and compared with the ones of epi-layers grown directly on Silicon and on 6H-SiC substrates. Short gate length transistors are fabricated using e-beam lithography. In spite of ohmic contact resistance of 0.6 Ω.mm, a saturated current density of 0.7 A/mm at a gate bias of +1V and a transconductance peak higher to 250 mS/mm for 75 nm T-shaped gate transistors are reached on structure with thick 3C-SiC template. Moreover, for the first time, transition frequencies f_T/f_max of 60/98 GHz are reported on such 3C-SiC template.

Abstract: In this work, the H3TRB performance of power modules with SiC MOSFET chips is investigated and compared to their silicon counterparts with similar electrical ratings. For this purpose, SiC MOSFETs and silicon IGBT chips are packaged in the same housing and with the same packaging technology and an H3TRB test is performed on both types of test devices. The results show that while both types exhibit an excellent H3TRB performance, the SiC MOSFETs had a significantly longer time to failure but also a wider failure distribution. Hence, the investigations presented in this paper confirm that properly designed SiC devices feature an equal or even better ruggedness against electro-chemical stress than standard silicon devics and are equally suitable for applications, which require operation in harsh environments.

Abstract: This paper presents experimental 1.2 kV, 10 A SiC thyristors with different amplifying gate design. In contrast to comparative devices (with simple gate) the amplifying gate thyristors show a characteristic snap-back and a higher gate current to trigger. Their gate-anode I-V characteristics comply with the underlying design constraint, regarding the resistances of pilot and main thyristor: (R_P > R_M). Moreover, the turn-on waveforms of well-designed amplifying gate thyristors reveal peak-shaped inversions in the gate current and voltage transients, providing clear evidence of the successive triggering of pilot and main thyristor.

Abstract: Similar charge to failure distributions with mean values of about 50 C/cm² were measured for planar SiC MOSFETs and MOS capacitors. Fast occurring and saturating negative flatband and threshold voltage drops were found in time resolved 1 second long pulsed gate current stress with I_G=1 mA/cm² at T=150 °C. No substantial difference in V_TH drift rate with V_GS=28 V at T=150 °C was found after about 10 s recovery period for I_G stressed devices compared with unstressed devices. Additionally, I_G stressed and unstressed devices did not differ in final V_TH shift at T=25 °C after V_GS=28 V stress (during 3 hrs or 31 hrs). More gate oxide reliability characterization is important to determine if 1 mA/cm² pulsed gate current stress creates any permanent changes to the SiC MOSFET device behaviour. Additionally, parametric shifts in V_TH and R_DSon was examined after long-term AC gate bias stress by a gate driver switching between-8V and 20V for four different commercially available SiC MOSFETs.

Abstract: The commercial success of silicon carbide (SiC) diodes and MOSFETs for the automotive industry has led many in the field to begin developing ultra-high voltage (UHV) SiC insulated gate bipolar transistors (IGBTs), rated from 6 kV to 30 kV, for future grid conversion applications. Despite this early interest, there has been little work conducted on the optimal layout for the SiC IGBT, most early work seeking to overcome difficulties in fabricating the devices without a P+ substrate. In this paper, numerical TCAD simulations are used to examine the link between the carrier lifetime of SiC IGBTs and their short circuit capability. For the planar devices, simulations show that increasing carrier lifetime from 1 to 10 μs, has not only a profound effect reducing on-state losses, but also increases short circuit withstand time (SCWT) by 39%. Two retrograde p-well designs are also investigated, the optimal device for SCWT having a 100 nm channel region of 5×10¹⁶ cm^-3, with this increasing to a peak value of 2×10¹⁸ cm^-3, in a 700 nm region beneath the channel.

Abstract: In this work the purpose of the simulations is to optimize a new large volume Silicon Carbide (SiC) detector for 14.1 MeV neutrons. The device has an active thickness obtained by epitaxial growth and an active area of 25 mm². In the first step of the simulations we compare SiC detector performance to Diamond and Silicon detectors, with the same geometric features. In the second step of the simulations we have found the best solution to improve the response of the detector for a fixed epitaxial layer thickness using an overlayer of aniline (C₆H₇N).

Abstract: This paper discusses the design and simulation of 4H-SiC semi-SJ structures producing results that are below the unipolar limit, whilst also ensuring practical and cost-effective realisation. The results demonstrate that a semi-SJ structure with a 10° sidewall angle increases the implantation window of the device by 45%, relative to the full-SJ, whilst maintaining a high V_BD of ~2 kV and a low R_ON,SP. This design facilitates a wide implantation window with a reduced trench aspect ratio, significantly improving the practical realisation of the device. It also offers softer reverse recovery characteristics as a result of both the angled trench sidewall and the n-bottom assist layer (n‑BAL) which allows for the structure to be depleted gradually.

Abstract: The development of robust, high-performance integrated circuits (ICs) will enable numerous potential NASA missions of current interest, including long-duration robotic missions exploring the 460°C surface of Venus. Currently, NASA is looking towards SiC-based devices to provide such a solution. However, the current NASA silicon carbide (SiC) JFET device with a channel length of 6 μm (recently fabricated Gen. 11 ICs) limits mission-relevant circuit capabilities. In this study, we combined experiments with simulations to explore two straightforward fabrication strategies (shallow n−and extended n+) to reduce the SiC JFET channel length while maintaining the turn-off behavior needed to realize 500°C circuit operation. COMSOL Multiphysics was used to simulate the transfer characteristics and maximum potential below the gate of a 4H-SiC nJFET at 500°C, and a 1 μm gate length nJFET with turn-off performance comparable to the state-of-the-art is suggested.

Abstract: A systematic germanium (Ge) and vanadium (V) study on 4H-SiC epitaxial layers is presented. Electrical results of TLM structures which were fabricated on these layers revealed that highly-doped Ge and V-implanted layers showed extremely low specific contact resistivity, down to 2 x 10^-7 Ω.cm². Current flow in the conducting state of Schottky barrier diodes has been successfully suppressed in some implanted layers, with highly V doped samples showing current density values of approximately 1 x 10^-5 Acm^-2 at 10 V. DLTS spectra reveal the presence of germanium and vanadium centers in the respective samples as well as novel peaks which are likely related to the formation of a novel GeN center.

Abstract: Metal-oxide-semiconductor capacitors with single and multi-layer high-K gate dielectrics on Si (0001) face of n-type 4H-SiC substrates have been investigated. Multi-layered nanolaminated gate-stack comprises alternating ultrathin (6nm) Al₂O₃ and HfO₂. A 5nm thick interfacial silicon oxynitride is deposited prior to laminated films to investigate interface trap properties and tuning of flat band voltage. Total thickness of gate-stack films including interfacial layer is 55nm. The thermal stability of multi-layered nanolaminated film is investigated using XTEM. Localized crystallization of HfO₂ is visible after RTA at 900°C while Al₂O₃ remains fully amorphous. Some of HfO₂ grains have extended into Al₂O₃ layer but was not able to crossover. The measured accumulation capacitance of 55nm thick gate dielectric gives an effective dielectric constant value of 9.6 and an equivalent oxide thickness of 22nm from high-frequency capacitance-voltage measurements. A positive flat band voltage ( of 12.2V and 10.6V are observed from both single layer HfO₂ and Al₂O₃ dielectrics, respectively due to presence of negatively charged oxygen interstitial defects generated during atomic layer deposition process. However, V_FB shifted towards negative voltage-7.6V for multi-layered Al₂O₃/HfO₂ stacks probably associated with positive Al and Hf interstitials at interface of Al₂O₃/HfO_2. Ultrathin interfacial oxynitride films is effective to reduce D_it to 3×10¹¹/eVcm² and tuning of V_FB. The breakdown field of stacked gate dielectric on 4H-SiC is 10.0 MV/cm.