Materials Science Forum Vol. 1062

Abstract: In high current applications that use several parallel-connected SiC MOSFETs (e.g., automotive traction inverters), optimal current sharing is integral to overall system reliability. Threshold voltage (VTH) variation in SiC MOSFETs is a prevalent reliability issue that can cause current mismatch in parallel-connected devices. Using experimental measurements and compact modelling, a technique has been developed for characterising the impact of VTH variation in up to 8 parallel-connected SiC MOSFETs. This model can predict the allowable VTH variation for optimal current sharing. It can also be used to evaluate the impact of other parameters, including gate driver synchronisation, on current sharing in parallel devices.

Abstract: This paper presents a Singular Point Source MOS (S-MOS) cell concept suitable for SiC MOSFETs targeting low conduction losses, low switching losses and high robustness. The S-MOS concept differs from standard Planar or Trench MOS cells in the manner by which the total channel width per device area is determined. For the proof of concept and device electrical performance evaluation, the paper will provide 2D and 3D TCAD simulations results for 1200V SiC MOSFETs including the S-MOS and reference planar and trench structures.

Abstract: Dealing with electronic devices for high reliability applications in terrestrial environments, neutron-induced Single Event Effects must be investigated. In this paper, the experimental observation of an atmospheric-like neutron-induced Single Event Burnout (SEB) on a packaged commercial SiC power MOSFET is presented after irradiation at ISIS-ChipIr. The effects of the SEB in the electrical properties of the MOSFET are established, and the SiC damaged zone is observed by scanning electron microscopy. Based on this failure analysis at the die level, the distinct stages during the SEB mechanism can be defined. The sensitive volume where the secondary particle deposited enough energy to trigger the SEB mechanism is identified and located inside the SiC n-drift epitaxial layer near the epitaxial layer/substrate junction.

Abstract: This work details two approaches with multi-epitaxial growth to create a vertical superjunction structure made of alternating pillars. One approach is a chain of very high energy implants, the other uses a preferred implantation direction to achieve a channeled profile. The manufactured devices show a breakdown voltage of 1000 V for channeled, two-step epi with total 4.9 μm thickness. 800 V for regular high energy implants using three epi steps of total 3.7 μm thickness. The measured Rsp was 0.7 mOhm*cm² for dies with size 0.018 cm². UIS and temperature measurement show reliable performance. The channeled implant looks favorable to reduce the number of process steps needed to create an efficient superjunction structure.

Abstract: In this work, body diode stress has been carried out for 1700 V 25 mΩ planar SiC MOSFETs. The epitaxial wafers were mapped with Infra-Red photoluminescence (IR-PL) to determine and localize the exact number of basal plane dislocations present in the drift layers of each die. The SiC MOSFETs were then packaged in groups with individual BPD counts in different bins ranging from 0 up to more than 30 per device. Pulsed body diode measurements with high currents of 250-400 A (about 1000-1600 A/cm²) were then performed with electrical characterization before and after to check for drift in key electrical parameters. Significantly increased R_DSon was found after high current stress from about 300 A for devices with BPDs. A physical analysis of the degraded devices by backside electroluminescence show the presence of several trapezoid-shaped patterns indicating the occurrence of bipolar degradation.

Abstract: We determine the effective critical breakdown field for 4H-SiC superjunction (SJ) devices and compare it to their conventional counterparts. Also, we investigate its dependence on SJ device structural parameters, such as drift layer thickness (t) and pillar width (W). In 4H-SiC SJ devices, the effective critical breakdown field was found to be around 30% lower than that of conventional devices owing to their longer ionization paths. In particular, the effective critical electric field varies as ξ_cr α t^-1/10 and ξ_cr α t^-1/6 for 4H-SiC SJ and conventional devices respectively but independent of pillar width and doping concentration for high aspect ratio devices (t/W > 10).

Abstract: We evaluate and compare the static and dynamic performances of four different 4H-SiC power MOSFETs (Conventional DMOS and UMOS, Superjunction (SJ) DMOS and UMOS FETs) from 0.6 to 10kV. The static on-state performance is determined by analytically calculating the specific on-resistance (R_ON,sp), while the dynamic switching performance is determined by extracting the specific gate charge (Q_G,sp) and switching energy loss per cycle (E_sw,cycle) using 2D device simulations. It has been found that the SJ UMOS FET exhibits at least a 31% (up to 53% at 0.6kV) reduction in the R_ON,sp · Q_G,sp Figure-of-Merit (FoM) compared to the SJ DMOS FET within the breakdown voltage rating range studied.

Abstract: Edge termination is a critical part of a power devices. Numerous edge termination types have been developed for silicon devices. Implementation of these termination architectures are not straightforward in SiC due to physical and processing specificities: lower junction depths, higher electric field, trench depth and shaping limitations, etc. Two main families of terminations are currently used in commercial devices, pure Field Guard Rings, and JTE + Rings combination. The increasing number of trench commercial devices requires new approaches based on etched rings filled with dielectrics or polysilicon. For epitaxied bipolar devices, MESA with bevel angle termination combined with JTE based architecture are also suitable. In any case, and especially regarding avalanche capability requirements, not only the termination architecture is relevant, but also the passivation type, the channel stopper design, the 3D design. As modelling using conventional tools is not fully reliable, specific complementary characterization methods are needed. For instance, micro-OBIC can be very effective to determine the electric field distribution in the periphery of the power devices.

Abstract: Experimental results from 15 kV-rated SiC DMOSFETs developed by GeneSiC Semiconductor are presented. A breakdown voltage of 16.7 kV is recorded, with < 200 nA leakage current at 15 kV. R_DS,ON in the range of 4-5 Ω, 12-15 Ω or 50-75 Ω were measured on MOSFETs with chip sizes of 25 mm², 16 mm² and 9 mm², respectively, with a lowest specific R_DS,ON of 238 mΩ-cm². The impact of MOSFET channel length and JFET width on the device performance is elucidated. Single-pulse avalanche energy = 22.1 J/cm² and t_AV=18.2 μs is achieved. V_G-+20 V gate stress applied at 175°C showed good V_TH stability with only a small 200-300 mV increase during the initial stages of the stress time.

Abstract: In this paper we report the progress of our SiC trench etch development using enhanced ICP-based etch technology. Computer modelling of the electric field strength in the gate oxide as a function of corner geometry was used to illustrate trench corner rounding as an effective method to avoid to high gate oxide field strengths. This is an effort to examine a major ongoing issue in device reliability, and to govern future device design.