Reduction of On-Resistance in 4H-SiC Multi-RESURF MOSFETs

Masato Noborio; Yuki Negoro; Jun Suda; Tsunenobu Kimoto

doi:10.4028/www.scientific.net/MSF.527-529.1305

Paper Titles

Switching Characteristics of SiC-MOSFET and SBD Power Modules
p.1289

Characterization of 4H-SiC MOSFETs Formed on the Different Trench Sidewalls
p.1293

The Characteristics of MOSFETs Fabricated on the Trench Sidewalls of Various Faces Using 4H-SiC (11-20) Substrates
p.1297

Fabrication of 4H-SiC p-Channel MOSFET with High Channel Mobility
p.1301

Reduction of On-Resistance in 4H-SiC Multi-RESURF MOSFETs
p.1305

Fabrication of 4H-SiC DIMOSFETs by High-Temperature (>1400°C) Rapid Thermal Oxidation and Nitridation Using Cold-Wall Oxidation Furnace
p.1309

A Study on the Reliability and Stability of High Voltage 4H-SiC MOSFET Devices
p.1313

Bias Stress-Induced Threshold-Voltage Instability of SiC MOSFETs
p.1317

Using a First Principles Coulomb Scattering Mobility Model for 4H-SiC MOSFET Device Simulation
p.1321

HomeMaterials Science ForumMaterials Science Forum Vols. 527-529Reduction of On-Resistance in 4H-SiC Multi-RESURF...

Reduction of On-Resistance in 4H-SiC Multi-RESURF MOSFETs

Abstract:

SiC lateral MOSFETs with multi-RESURF structures have been fabricated by a self-aligned process. The “multi-RESURF” means “double RESURF” and “buried-p RESURF” structures, which have the buried-p region at the top and at the middle of RESURF region, respectively. The increase of net RESURF dose and the decrease of channel length lead to the reduced on-resistance. The “buried-p RESURF” MOSFETs have higher on-resistances than the “double RESURF” MOSFETs, due to the resistance of parasitic JFET inside the RESURF region. The dose designing for double RESURF MOSFETs has been optimized by using device simulation. A double RESURF MOSFET exhibits a breakdown voltage of 750 V and an on-resistance of 52 m/cm2.

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Periodical:

Materials Science Forum (Volumes 527-529)

Pages:

1305-1308

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.527-529.1305

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Online since:

October 2006

Authors:

Masato Noborio, Yuki Negoro, Jun Suda, Tsunenobu Kimoto

Keywords:

Device Simulation, Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), Power Device, Reduced-Surface-Field RESURF, Self-Aligned Process

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