Reduction of On-Resistance in 4H-SiC Multi-RESURF MOSFETs
SiC lateral MOSFETs with multi-RESURF structures have been fabricated by a self-aligned process. The “multi-RESURF” means “double RESURF” and “buried-p RESURF” structures, which have the buried-p region at the top and at the middle of RESURF region, respectively. The increase of net RESURF dose and the decrease of channel length lead to the reduced on-resistance. The “buried-p RESURF” MOSFETs have higher on-resistances than the “double RESURF” MOSFETs, due to the resistance of parasitic JFET inside the RESURF region. The dose designing for double RESURF MOSFETs has been optimized by using device simulation. A double RESURF MOSFET exhibits a breakdown voltage of 750 V and an on-resistance of 52 m/cm2.
Robert P. Devaty, David J. Larkin and Stephen E. Saddow
M. Noborio et al., "Reduction of On-Resistance in 4H-SiC Multi-RESURF MOSFETs", Materials Science Forum, Vols. 527-529, pp. 1305-1308, 2006