Enhanced Annealing of the Main Lifetime Limiting Defect in Thick 4H-SiC Layers

L. Storasta; Tetsuya Miyazawa; Hidekazu Tsuchida

doi:10.4028/www.scientific.net/MSF.600-603.477

Paper Titles

Raman Investigation of the Effect of Metal Impurities at Gettering Sites on Phonon and Electron Related Properties of 4H-SiC n-n⁺ Junctions
p.465

Nitrogen Passivation of (0001) 4H-SiC Dangling Bonds
p.469

Origin of Giant Step Bunching on 4H-SiC (0001) Surfaces
p.473

Enhanced Annealing of the Main Lifetime Limiting Defect in Thick 4H-SiC Layers
p.477

Impact of 4H-SiC Substrate Defectivity on Epilayer Injected Carrier Lifetimes
p.481

Generation and Recombination Carrier Lifetimes in 4H SiC Epitaxial Wafers
p.485

Variations in the Measured Carrier Lifetimes of n^- 4H-SiC Epilayers
p.489

Investigation of the Internal Carrier Distribution in 4H-SiC Pin-Diodes by Laser Absorption Experiments
p.493

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Enhanced Annealing of the Main Lifetime Limiting Defect in Thick 4H-SiC Layers

Abstract:

We have studied annealing of the main lifetime limiting defect Z1/2 in thick 4H-SiC epilayers by the application of carbon-implantation/annealing method. Examination of different implantation doses and annealing temperatures showed that finding the optimum conditions is crucial for obtaining carrier trap concentration below 1011 cm-3 in the whole 100 μm epilayer. The carrier lifetime increased from under 200 ns to over 1 μs at room temperature in the samples prepared by optimized carbon-implantation/annealing technique. Fabrication of pin diodes from the improved thick 4H-SiC epilayers confirmed the enhanced conductivity modulation and suitability of this technique for high-voltage bipolar SiC devices.