Silicon Carbide Vertical JFET with Self-Aligned Nickel Silicide Contacts

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Abstract:

Trenched implanted vertical JFETs (TI-VJFETs) with self-aligned gate and source contacts were fabricated on commercial 4H-SiC epitaxial wafers. Gate regions were formed by aluminium implantation through the same silicon oxide mask which was used for etching mesa-structures. Self-aligned nickel silicide source and gate contacts were formed using a silicon oxide spacer formed on mesa-structure sidewalls by anisotropic thermal oxidation of silicon carbide followed by anisotropic reactive ion etching of oxide. Fabricated normally-on 4H-SiC TI-VJFETs demonstrated low gate leakage currents and blocking voltages exceeding 200 V.

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Periodical:

Materials Science Forum (Volumes 679-680)

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670-673

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March 2011

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© 2011 Trans Tech Publications Ltd. All Rights Reserved

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