Silicon Carbide Vertical JFET with Self-Aligned Nickel Silicide Contacts
Trenched implanted vertical JFETs (TI-VJFETs) with self-aligned gate and source contacts were fabricated on commercial 4H-SiC epitaxial wafers. Gate regions were formed by aluminium implantation through the same silicon oxide mask which was used for etching mesa-structures. Self-aligned nickel silicide source and gate contacts were formed using a silicon oxide spacer formed on mesa-structure sidewalls by anisotropic thermal oxidation of silicon carbide followed by anisotropic reactive ion etching of oxide. Fabricated normally-on 4H-SiC TI-VJFETs demonstrated low gate leakage currents and blocking voltages exceeding 200 V.
Edouard V. Monakhov, Tamás Hornos and Bengt. G. Svensson
K. Vassilevski et al., "Silicon Carbide Vertical JFET with Self-Aligned Nickel Silicide Contacts", Materials Science Forum, Vols. 679-680, pp. 670-673, 2011