Materials Science Forum Vol. 924

Abstract: The growth of diamond films on different substrates has been studied extensively to support the emerging technologies ranging from mechanical to nano/microelectronics. It is known that the performance of these applications is affected by diamond film properties, such as structure and morphology. Using chemical vapor deposition (CVD) technique, we have deposited ultrananocrystalline diamond (UNCD) and microcrystalline diamond (MCD) films on 4H-SiC substrates and investigated their basic material properties. The understanding and exploitation of the material properties are fundamental to evaluate the potential of UNCD-on-SiC and MCD-on-SiC structures for fabrication of electronic devices and sensors.

Abstract: Schottky diodes fabricated on free-standing B doped monocrystalline diamond substrate have been investigated. As expected, reverse leakage current due to Schottky barrier lowering has been observed due to the high electric field at the metal-semiconductor interface. Forward current is highest under operating temperatures between 400 and 450K due to incomplete ionization hole mobility dependence on temperature. It is demonstrated that the static device characteristics in the temperature range from 300K to 450K can be modelled by parametrizing an analytical introduced for unipolar SiC and Si diodes.

Abstract: Lateral gate depletion expansion towards drain contact has been analyzed on p-type diamond metal-semiconductor field effect transistor by electron beam induced current. The investigation was restricted to a closed channel to simplify the study and to directly observe the expansion of the lateral depletion region. The experimental data agreed with the theoretical model given in the literature.

Abstract: This paper deals with investigation and fabrication of 4H-SiC MOSFETs with a high-k dielectric close to ZrSiO₄. We are looking for the optimal stochiometry in order to obtain full benefits of its large bandgap, a k value higher than that of SiO₂, thermodynamic stability on SiC, a good interface quality and process compatibility with SiC technology. Several Si/Zr ratios have been tested with the purpose of obtaining the most favorable dielectric configuration. The first test devices have been manufactured successfully with a stack gate dielectric consisting of a thin SiO₂ interlayer and a Zr_xSi_yO_z (theoretical Si/Z=0.7) layer on top.

Abstract: Anodization of silicon carbide (SiC) in hydrofluoric acid (HF) solutions is a promising way to etch this material which is very resistant against traditional chemical etching methods. Moreover, it has been shown that several reproducible porous SiC morphologies can be performed varying anodization conditions (current density, electrolyte composition, UV lighting) and/or substrate properties (doping type and level). This paper proposes a state of the art of porous SiC etching in GREMAN and a presentation of the morphologies achievable using anodization in HF based electrolytes.

Abstract: This report describes more than 5000 hours of successful 500 °C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 °C. After 100 hours of 500 °C burn-in, the circuits (except for 2 failures) exhibit less than 10% change in output characteristics for the remainder of 500 °C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460 °C in comparison to what is observed for Earth-atmosphere oven testing at 500 °C.

Abstract: The increasing demand for electronics in harsh environment applications has inspired investigation of silicon carbide (SiC)-based devices and circuits, due to its superior electrical properties. Several researchers have demonstrated the viability of 4H-SiC control circuitry by developing small scale logic circuits entirely in 4H-SiC. However, development and design of memory elements, which is a critical component in any electronic system, is still not fully explored. To bridge this gap, this paper presents, a complete bipolar, static random access memory (SRAM) column that includes the memory cell and the peripheral circuitry, designed to exploit the unique properties of SiC. Simulation results for the proposed memory show stable operation across a wide range of temperatures (27 °C – 500 °C) with good noise margins and access speeds while running at a supply voltage as low as 5 V. This work validates the potential of developing memory architectures in 4H-SiC, paving the way for realizing small-sized digital systems for harsh environments.

Abstract: This work presents the design and electrical characterization of in-house-fabricated 2-input NAND gate. The monolithic bipolar 2-input NAND gate employing transistor-transistor logic (TTL) is demonstrated in 4H-SiC and operates over a wide range of temperature and supply voltage.The fabricated circuit was characterized on the wafer by using a hot-chuck probe-station from 25 °C up to 500 °C. The circuit is also characterized over a wide range of voltage supply i.e. 11 to 20 V. The output-noise margin high (NM_H) and output-noise margin low (NM_L) are also measured over a wide range of temperatures and supply voltages using voltage transfer characteristics (VTC). The transient response was measured by applying two square waves of, 5 kHz and 10 kHz. It is demonstrated that the dynamic parameters of the circuit are temperature dependent. The 2-input TTL NAND gate consumes 20 mW at 500 °C and 15 V.

Abstract: The DC electrical behavior of n-type 4H-SiC resistors used for realizing 500 °C durable integrated circuits (ICs) is studied as a function of substrate bias and temperature. Improved fidelity electrical simulation is described using SPICE NMOS model to simulate resistor substrate body bias effect that is absent from the SPICE semiconductor resistor model.

Abstract: Two characterization methods are compared in terms of their suitability for predicting the electrical behavior of non-uniform Ni/4H-SiC Schottky contacts up to 450°C, using data measured at lower temperatures. These techniques are based on the established Gaussian distribution of barrier heights model and a recently proposed discrete barrier distribution model, respectively. Two samples with different degrees of contact inhomogeneity are measured and their forward characteristics are fitted using both techniques. The Gaussian distribution approach is shown to accurately fit experimental data only for the nearly-uniform sample, while requiring the extraction of two separate barrier height values from measurements in the room-250°C range, only. When attempting to use this method to characterize the sample with strong non-uniformity, fitting accuracy (given by R²) drops under 90%. In contrast, the discrete barrier distribution technique is proven able to forecast the electrical behavior of both samples (with R² > 99% in most cases), over the entire room-450°C range, using a single Schottky barrier for each device (1.61V, corresponding to a Ni₂Si Schottky contact and 0.9V, afferent to a Ni metallization).