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TCAD Optimisation of 4H-SiC Channel-Doped MOSFET with P-Polysilicon Gate
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Hysteresis in Transfer Characteristics in 4H-SiC Depletion/Accumulation-Mode MOSFETs
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HomeMaterials Science ForumMaterials Science Forum Vols. 389-393TCAD Optimisation of 4H-SiC Channel-Doped MOSFET...

TCAD Optimisation of 4H-SiC Channel-Doped MOSFET with P-Polysilicon Gate

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Silicon Carbide and Related Materials 2001

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Periodical:

Materials Science Forum (Volumes 389-393)

Pages:

1085-1088

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.389-393.1085

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Online since:

April 2002

Authors:

Kazuhiro Adachi, C. Mark Johnson, Kazuo Arai, Kenji Fukuda, Shinsuke Harada, Takashi Shinohe

Keywords:

4H-SiC, B-MOSFET, Buried Channel, Channel Mobility, Channel-Doped, C-MOSFET, Dit, Interface States (or Traps), Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), Modeling, Simulation, Surface Mobility, TCAD

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© 2002 Trans Tech Publications Ltd. All Rights Reserved

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