Silicon Carbide and Related Materials 2006

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Authors: Chia Ching Chen, Alton B. Horsfall, Nicolas G. Wright, Konstantin Vassilevski
Abstract: The formation of two-dimensional electron gases (2DEG) at the polytypic 6H/3C heterojunction is investigated. The main of study was to obtain the properties of the 3C/6H structure using Technology Computer Aided Design (TCAD) software. The electron-density distribution and conduction band profile in 6H/3C SiC heterojunction are calculated as a function of temperature. Simulation of these hetero-junctions has concentrated on the I-V behaviour over a range of temperatures between 350 and 650 K. We show that the device characteristics are substantially degraded at high temperatures and this will limit the use of these devices to moderate temperature applications.
Authors: Siddharth Potbhare, Neil Goldsman, Gary Pennington, Aivars J. Lelis, J.M. McGarrity
Abstract: SiC MOSFETs have very large interface trap densities which degrade device performance. The effect of traps on inversion layer mobility and inversion charge concentration has been studied, and mobility models suitable for inclusion in Drift-Diffusion simulators have been developed for steady state operation of SiC MOSFET devices. Here, we attempt to model the transient behavior of SiC MOSFETs, and at the same time, extract the time constants for the filling and emptying of interface traps. As compared to the inversion layer, interface traps in SiC MOSFETs are slow in reacting to change in gate bias. So, at the positive edge of a gate pulse, we see a large current in the MOSFET, which then decays slowly to the steady state value as the interface traps fill up. We have developed a generation/recombination model for minority carriers in a SiC MOSFET based on the Shockley-Read-Hall recombination model for electrons and holes. In our model, the generation/recombination takes place between minority carriers in the inversion layer, and the traps at the SiC-SiO2 interface. Comparing our simulated current vs. time curves to experiment, we have been able to extract time constants for the filling and emptying of traps at the SiC-SiO2 interface.
Authors: Gerald Soelkner, Winfried Kaindl, Michael Treu, Dethard Peters
Abstract: Cosmic radiation has been identified as a decisive factor for power device reliability. Energetic neutrons create ionizing recoils within the semiconductor substrate which may lead to device burnout. While this failure mode has gained widespread acceptance for power devices based on silicon the question whether a similar mechanism could also lead to failure of SiC devices was left to be debated. Radiation hardness intrinsic to the SiC material was generally assumed but as experimental data was scarce reliability problems due to radiation-induced device failure could not be ruled out. Recent accelerated testing results now show that cosmic radiation will indeed affect the reliability of SiC power devices, as it is the case for its silicon counterpart, but the problem can be contained very effectively by device design.
Authors: Tsuyoshi Yamamoto, Takeshi Endo, Nobuyuki Kato, Hiroki Nakamura, Toshio Sakakibara
Abstract: 4H-SiC SBDs have been commercialized for power application devices. However, the maximum current of these SBDs is 20A. In this work, we designed a JBS (junction barrier Schottky) diode structure and the fabrication processes to be optimized. The current and breakdown voltage were over 100 A and 660 V at Ir = 1 mA/cm2, respectively. The recovery characteristics of the JBS diode are much superior to those of the Si-FRD while it is comparable to those of the commercially available SiC-SBD at elevated temperatures up to 125°C..
Authors: S.J. Kim, Y.S. Choi, S.J. Yu, Sang Cheol Kim, Wook Bahng, K.H. Lee
Abstract: This paper demonstrates the breakdown voltage characteristics of different edge termination structures including aluminum (Al)-deposited guard ring and Al-deposited guard ringassisted field limiting ring (FLR) for a 4H silicon carbide (SiC) Schottky barrier diode (SBD). In order to investigate the application feasibility of the Al-deposited junction termination to a high breakdown voltage SiC-SBD, two types of SiC-SBDs are fabricated using conventional photolithography, electron beam evaporation, and thermal treatment techniques without ion implantation and thermal oxidation procedures. The breakdown voltage characteristics of the SiCSBDs are significantly dependent on the Al-deposited edge termination. The SiC-SBD without the Al-deposited edge termination shows less than 250 V breakdown voltage, while the Al-deposited guard ring and Al-deposited guard ring-assisted FLR structures show roughly 700 V and 1200 V breakdown voltages, respectively. The prominent improvement in the breakdown voltage characteristics is attributed to the electric field lowering at the Schottky contact edge by the Al deposition edge termination.
Authors: Gheorghe Brezeanu, M. Brezeanu, F. Udrea, G. Amaratunga, C. Boianceanu, M. Badila, Konstantinos Zekentes, Adi Visoreanu
Abstract: A classical implementation of the field plate technique is the oxide ramp termination. This paper presents for the first time a comparison between SiC and diamond Schottky barrier diodes (SBD) using this termination. The influences of the ramp angle and oxide thickness on the diodes electrical performance are investigated for both punch-through (PT) and non punch-through (nPT) structures. The efficiency of the termination is also evaluated.
Authors: S.J. Kim, S. Kim, Sang Cheol Kim, In Ho Kang, K.H. Lee, T. Matsuoka
Abstract: We have investigated the field limiting ring (FLR) geometry dependence of breakdown voltage characteristics for a junction barrier Schottky (JBS)-assisted FLR SiC-SBD. The SiC-SBDs having a guard ring-assisted FLR surrounding a Schottky contact edge and an internal ring inside Schottky contact were fabricated. The breakdown voltage characteristics of the JBS-assisted FLR SiC-SBD are significantly dependent on the width, spacing, and number of FLR. The breakdown voltage characteristic is improved as either the FLR width and FLR number increase or the FLR spacing decreases. Approximately 1650 V maximal breakdown voltage, corresponding to 82% ideal breakdown voltage, is observed with seven FLRs having 5 2m width and 1 2m spacing.
Authors: Konstantin Vassilevski, Irina P. Nikitina, Alton B. Horsfall, Nicolas G. Wright, Anthony G. O'Neill, Keith P. Hilton, A.G. Munday, A.J. Hydes, Michael J. Uren, C. Mark Johnson
Abstract: High voltage 4H-SiC Schottky diodes with single-zone junction termination extension (JTE) have been fabricated and characterised. Commercial 4H-SiC epitaxial wafers with 10, 20 and 45 +m thick n layers (with donor concentrations of 3×1015, 8×1014 and 8×1014 cm-3, respectively) were used. Boron implants annealed under argon flow at 1500°C for 30 minutes, without any additional protection of the SiC surface, were used to form JTE’s. After annealing, the total charge in the JTE was tuned by reactive ion etching. Diodes with molybdenum Schottky contacts exhibited maximum reverse voltages of 1.45, 3.3 and 6.7 kV, representing more than 80% of the ideal avalanche breakdown voltages and corresponding to a maximum parallel-plane electric field of 1.8 MV/cm. Diodes with a contact size of 1×1 mm were formed on 10 +m thick layers (production grade) using the same device processing. Characterisation of the diodes across a quarter of a 2-inch wafer gave an average value of 1.21 eV for barrier heights and 1.18 for ideality factors. The diodes exhibited blocking voltages (defined as the maximum voltage at which reverse current does not exceed 0.1 mA) higher than 1 kV with a yield of 21 %.
Authors: Akimasa Kinoshita, Takashi Nishi, Tsutomu Yatsuo, Kenji Fukuda
Abstract: Ion implantation and a subsequent annealing at high temperature are required for fabricating a high voltage Schottky Barrier Diode (SBD) with a field limiting ring (FLR) or a junction termination extension (JTE), but high temperature annealing degrades surface condition of a SiC substrate and induces a degradation of electronic characteristics of a fabricated SBD. To avoid a degradation of SBD electronic characteristics after high temperature annealing, the method of removing a degraded layer from a SiC surface by sacrificial oxidation after high temperature annealing is studied. In this study, we studied the relationship between the improvement of SBD electronic characteristics and the thickness of sacrificial oxide grown after high temperature annealing. 9~12 SBD without edge termination were fabricated on a SiC substrate of 4mm×4mm. The ratio of good chips to all chips (9~12 SBD) increases with increasing total thickness of sacrificial oxide grown after high temperature annealing at 1800oC for 30 s, where an SBD with a leakage current less than 1μA/cm2 at reverse voltage of –100V was defined as a good chip. We applied this process growing sacrificial oxide of 150nm after high temperature annealing to fabricate the SBD with an FLR structure designed with 600V blocking voltage on a Si-face SiC substrate. The SBD with an FLR structure through this process of 150 nm sacrificial oxide is low leakage current of less than 1μA/cm2 at reverse voltage of –100V and achieves 600V blocking voltage, however, the SBD with an FLR structure without the process of sacrificial oxide after high temperature annealing is high leakage current at reverse voltage of –100V. It is shown that this process growing sacrificial oxide after high temperature annealing is useful to fabricate an SBD with an FLR structure.
Authors: Chiharu Ota, Johji Nishio, Tetsuo Hatakeyama, Takashi Shinohe, Kazutoshi Kojima, Shin Ichi Nishizawa, Hiromichi Ohashi
Abstract: The calculation for 4H-SiC floating junction Schottky barrier diodes (Super-SBDs) was carried out by device simulation and the optimized device structure was fabricated. The best characteristics of the Super-SBDs were breakdown voltage of 2700V and the specific on-resistance of 2.57m*cm2. The world record of Bariga’s Figure of Merit (BFOM) for SiC-SBD expressed by 4Vbd 2/Ron was improved to 11,354MW/cm2.

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