Materials Science Forum Vols. 556-557

Abstract: The electrical characteristics of a SiC-MESFET are affected by the channel structure characteristics, such as impurity density and thickness. MESFETs fabricated with ion implantation technique, can form thinner and higher doped channel layers than those fabricated with conventional epitaxial growth, thus improve RF characteristics of MESFETs. We calculated the doping profile of the channel layer for an ion implanted SiC-MESFET using a simulator and then fabricated a SiC-MESFET with the same doping profile as obtained from the simulation. The ion implanted SiC-MESFET operated successfully and had the same electrical characteristics as the epitaxial SiC-MESFET. We demonstrated the effectiveness of one-step implantation channel layer for the ion implanted SiC-MESFET.

Abstract: Electronic measurement coupled with device and material modeling of lateral longchannel 4H-SiC MOSFETs is used to investigate current saturation. Observed increases in drain current with increases in temperature are shown to result from a reduction in interface charge trapping. If trapping is ignored, the saturation current is predicted to decrease with increasing temperature as a result of interface phonon scattering.

Abstract: 4H-SiC lateral MOSFETs with a double reduced surface field (RESURF) structure have been fabricated in order to reduce drift resistance. A two-zone RESURF structure was also employed in addition to double RESURF structure for achieving both high breakdown voltage and low on-resistance. After device simulation for dose optimization, 4H-SiC two-zone double RESURF MOSFETs have been fabricated. The fabricated MOSFETs block 1380 V and exhibit a low on-resistance of 66 m1cm2 (including a drift resistance of 24 m1cm2) at a gate oxide field of 3 MV/cm. The figure-of-merit of present device is about 29 MW/cm2, which is the best performance among any lateral MOSFETs. The drift resistance of the fabricated double RESURF MOSFETs is only 50 % or even lower than that of single RESURF MOSFETs. Temperature dependence of device characteristics is also discussed.

Abstract: SiC MOSFETs are characterized with a specific on-resistance of 8 m
⋅cm2 at room temperature and a blocking voltage of 1500 V. Due to the negative shift in the threshold voltage, devices typically show a reduction in on-resistance with temperature. However, this work shows that a positive resistance temperature coefficient can be achieved by proper device design. SiC MOSFETs were characterized for use in high-frequency resonant converters, where an important switching device figure of merit is the product of the device on-resistance and output capacitance (Ron×Coss). For devices with an active area of 3.6×10-3 cm2, the output capacitance is 12.5 pF at a drain bias of 270V. Thus, these device achieve a resonant converter figure of merit Ron×Coss = 28
⋅pF at room temperature and 34
⋅pF at 150°C, better than commercial silicon superjunction devices operating at the same temperatures.

Abstract: A double delta-doped channel 4H-SiC MESFET is proposed to kick out degradation of the DC and RF performances caused by the surface traps, by forming a quantum-well-like potential well and separating an effective channel from the surface. To obtain an optimum device structure, the DC and RF performances of double delta-doped channel MESFETs having various delta-doping concentrations but the same pinch-off voltage with that of conventional MESFET were also investigated. The SilvacoTM simulation results show that the double delta-doped channel MESFET achieved more improvement of the drain current, the cut-off frequency, and the maximum oscillation frequency for higher delta-doping concentration near the gate. In all cases, DC and RF performances for double delta-doped channel MESFETs are much improved than those of the conventional MESFET.

Abstract: Inversion-type 4H-SiC power MOSFETs using p-body implanted with retrograde profiles have been fabricated. The Al concentration at the p-body surface (Nas) is varied in the range from 5×1015 to 2×1018 cm-3. The MOSFETs show normally-off characteristics. While the Ron is 3 cm2 at Eox = (Vg-Vth)/dox ≅ 3 MV/cm for the MOSFET with the Nas of 2×1018 cm-3, the Ron is reduced by a decrease in the Nas and 26 mcm2 is attained for the device with the Nas of 5×1015 cm-3. The inversion channel mobility and threshold voltage are improved with a decrease in the Nas. By modifying the structural parameter of the MOSFET, a still smaller Ron of 7 mcm2 is achieved with a blocking voltage of 1.3 kV.

Abstract: While there have been numerous reports of short-term transistor operation at 500 °C or above, these devices have previously not demonstrated sufficient long-term operational durability at 500 °C to be considered viable for most envisioned applications. This paper reports the development of SiC field effect transistors capable of long-term electrical operation at 500 °C. A 6H-SiC MESFET was packaged and subjected to continuous electrical operation while residing in a 500 °C oven in oxidizing air atmosphere for over 2400 hours. The transistor gain, saturation current (IDSS), and on-resistance (RDS) changed by less than 20% from initial values throughout the duration of the biased 500 °C test. Another high-temperature packaged 6H-SiC MESFET was employed to form a simple one-stage high-temperature low-frequency voltage amplifier. This single-stage common-source amplifier demonstrated stable continuous electrical operation (negligible changes to gain and operating biases) for over 600 hours while residing in a 500 °C air ambient oven. In both cases, increased leakage from annealing of the Schottky gate-to-channel diode was the dominant transistor degradation mechanism that limited the duration of 500 °C electrical operation.

Abstract: In prior work we have proposed a mobility model for describing the mobility degradation observed in SiC MOSFET devices, suitable for being implemented into a commercial simulator, including Coulomb scattering effects at interface traps. In this paper, the effect of temperature and doping on the channel mobility has been modelled. The computation results suggest that the Coulomb scattering at charged interface traps is the dominant degradation mechanism. Simulations also show that a temperature increase implies an improvement in field-effect mobility since the inversion channel concentration increases and the trapped charge is reduced due to bandgap narrowing. In contrast, increasing the substrate impurity concentration further degrades the fieldeffect mobility since the inversion charge concentration decreases for a given gate bias. We have good agreement between the computational results and experimental mobility measurements.

Abstract: This report investigates the advantages of high-k materials as gate dielectrics for high power SiC trench MOSFET devices, by means of TCAD simulation. The study makes a comparison between the breakdown characteristics of gate dielectrics comprising SiO2, HfO2 and TiO2. I-V and Transfer functions show forward characteristics with on-state resistivity of 8.27 m*⋅cm2, 8.65 m*⋅cm2, 15.8 m*⋅cm2 for the respective devices, at a gate voltage of 20 V. The threshold voltage is 10 V for all devices. The blocking voltage for the HfO2 and TiO2 is increased from 1800 V (for the SiO2 device) to 2200 V. With a peak electric field of 12 MV/cm through the oxide of the SiO2 device is reduced to 3.2 MV/cm for the HfO2 and 2.3 MV/cm for the TiO2 devices.