Silicon Carbide and Related Materials 2006

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Authors: Jeong Hyuk Yim, Ho Keun Song, Jeong Hyun Moon, Han Seok Seo, Jong Ho Lee, Hoon Joo Na, Jae Bin Lee, Hyeong Joon Kim
Abstract: Planar MESFETs were fabricated on high-purity semi-insulating (HPSI) 4H-SiC substrates. The saturation drain current of the fabricated MESFETs with a gate length of 0.5 μm and a gate width of 100 μm was 430 mA/mm, and the transconductance was 25 mS/mm. The maximum oscillation frequency and cut-off frequency were 26.4 GHz and 7.2 GHz, respectively. The power gain was 8.4 dB and the maximum output power density was 2.8 W/mm for operation of class A at CW 2 GHz. MESFETs on HPSI substrates showed no current instability and much higher output power density in comparison to MESFETs on vanadium-doped SI substrates.
Authors: Hyung Seok Lee, Martin Domeij, Carl Mikael Zetterling, Mikael Östling
Abstract: 4H-SiC BJTs have been fabricated with varying geometrical designs. The maximum value of the current gain was about 30 at IC=85 mA, VCE=14 V and room temperature (RT) for a 20 μm emitter width structure. A collector-emitter voltage drop VCE of 2 V at a forward collector current 55 mA (JC = 128 A/cm2) was obtained and a specific on-resistance of 15.4 m2·cm2 was extracted at RT. Optimum emitter finger widths and base-contact implant distances were derived from measurement. The temperature dependent DC I-V characteristics of the BJTs have been studied resulting in 45 % reduction of the gain and 75 % increase of the on-resistance at 225 oC compared to RT. Forward-bias stress on SiC BJTs was investigated and about 20 % reduction of the initial current gain was found after 27.5 hours. Resistive switching measurements with packaged SiC BJTs were performed showing a resistive fast turn-on with a VCE fall-time of 90 ns. The results indicate that significantly faster switching can be obtained by actively controlling the base current.
Authors: Qing Chun Jon Zhang, Charlotte Jonas, Bradley Heath, Mrinal K. Das, Sei Hyung Ryu, Anant K. Agarwal, John W. Palmour
Abstract: SiC IGBTs are suitable for high power, high temperature applications. For the first time, the design and fabrication of 9 kV planar p-IGBTs on 4H-SiC are reported in this paper. A differential on-resistance of ~ 88 m(cm2 at a gate bias of –20 V is achieved at 25°C, and decreases to ~24.8 m(cm2 at 200°C. The device exhibits a blocking voltage of 9 kV with a leakage current density of 0.1 mA/cm2. The hole channel mobility is 6.5 cm2/V-s at room temperature with a threshold voltage of –6.5 V resulting in enhanced conduction capability. Inductive switching tests have shown that IGBTs feature fast switching capability at both room and elevated temperatures.
Authors: Sei Hyung Ryu, Sumi Krishnaswami, Brett A. Hull, Bradley Heath, Fatima Husna, Jim Richmond, Anant K. Agarwal, John W. Palmour, James D. Scofield
Abstract: High temperature characteristics of 4H-SiC power JFETs and DMOSFETs are presented in this paper. Both devices are based on pn junctions in 4H-SiC, and are capable of 300oC operation. The 4H-SiC JFET showed very predictable, well understood temperature dependent characteristics, because the current conduction depends on the drift of electrons in the bulk region, which is not restricted by traps in the MOS interface or at the pn junctions. On the other hand, in a 4H-SiC DMOSFET, electrons must flow through the MOS inversion layer with a very high interface state density. At high temperatures, the transconductance of the device improves and threshold voltage shifts negative because less electrons are trapped in the interface states, resulting in a much lower MOS channel resistance. This cancels out the increase in drift layer resistance, and as a result, a temperature insensitive on-resistance can be demonstrated. The performance of the two devices are compared, and a discussion of issues for their high temperature application is presented.
Authors: Satoshi Tanimoto, Tatsuhiro Suzuki, Akihiro Hanamura, Masakatsu Hoshi, Toshiro Shinohara, Kazuo Arai
Abstract: This paper discusses critical reliability issues and their countermeasures for vertically structured poly-Si gate n-channel power MOSFETs (DMOS) on 4H-SiC when operated at an elevated temperature of more than 300°C for a long period of time. Two destructive failures were identified in a storage life test at 500°C: a short-circuit between the source and the gate and a disconnection at the n+ source contact. The former was caused by interlayer dielectric erosion and/or Al spearing into the poly-Si gate; the latter was caused by the disappearance of the NiSix contact layer. Effective and practical countermeasures were devised and implemented. Device lifetime against the three different failure mechanisms was improved in every case by at least one order of magnitude.
Authors: Mitsuo Okamoto, Mieko Tanaka, Tsutomu Yatsuo, Kenji Fukuda
Abstract: It is of great importance to investigate the electrical properties of SiC p-channel MOSFETs for development of SiC CMOS technology. In the present report, we investigated dependences of electrical properties of the SiC p-channel MOSFETs on SiC poly-types. The on-state characteristics (channel mobility, threshold voltage, and temperature dependences) for the 4H- and 6H-SiC p-channel MOSFETs showed similar behavior, although those of 4H-SiC n-channel MOSFETs are usually quite different from those of 6H-SiC. These results might be caused by the similar SiC MOS interface state distribution around the valence band edge.
Authors: Shiro Hino, Tomohiro Hatayama, Naruhisa Miura, Tatsuo Oomori, Eisuke Tokumitsu
Abstract: We have fabricated and characterized MOS capacitors and lateral MOSFETs using Al2O3 as a gate insulator. Al2O3 films were deposited by metal-organic chemical vapor deposition (MOCVD) at temperatures as low as 190 oC using tri-ethyl-aluminum and H2O as precursors. We first demonstrate from the capacitance – voltage (C-V) measurements that the Al2O3/SiC interface has lower interface state density than the thermally-grown SiO2/SiC interface. No significant difference was observed between X-ray photoelectron spectroscopy (XPS) Si 2p spectrum from the Al2O3/SiC interface and that from the SiC substrate, which means the SiC substrate was not oxidized during the Al2O3 deposition. Next, we show that the fabricated lateral SiC-MOSFETs with Al2O3 gate insulator have good drain current – drain voltage (ID-VD) and drain current – gate voltage (ID-VG) characteristics with normally-off behavior. The obtained peak values of field-effect mobility (μFE) are between 68 and 88 cm2/Vs.
Authors: Kin Kiong Lee, Michael Laube, Takeshi Ohshima, Hisayoshi Itoh, Gerhard Pensl
Abstract: In this paper we give a comparative study of two types of gate oxidation of n-channel 6HSiC MOSFETs. One set of transistors was fabricated using pyrogenic oxidation with no postoxidation annealing, and for the second set the oxide was grown in dry O2 with post-oxidation annealing. The lateral MOSFETs show a Hall mobility of ~ 75 cm2/Vs which is essentially same for both types of oxide. From the IV characteristics curves, the latter devices exhibit an average effective channel mobility of 72 (± 5) cm2/Vs, whereas the former has a value of 30 (± 3) cm2/Vs. From the capacitance and conductance measurements, the interface trap density for pyrogenicgrown oxide using is roughly a factor of 2 greater than those grown by dry oxidation. We found that the pyrogenic post-oxidation anneal at 1073K helps to reduce the interface states density and improves the effective channel mobility of 6H-SiC MOSFETs.
Authors: G. Gudjónsson, Fredrik Allerstam, Per Åke Nilsson, Hans Hjelmgren, Einar Ö. Sveinbjörnsson, Herbert Zirath, T. Rödle, R. Jos
Abstract: We present new results on 4H-SiC RF power MOSFETs. By improvements in device layout we obtain better high frequency performance compared to the first generation of devices. An extrinsic transition frequency fT=11.4 GHz was achieved and fmax=11.2 GHz for a device with 0.5 µm nominal channel length. Functional devices with 0.3 µm nominal channel length were also made. These devices gave fT=15.1 GHz and fmax=19.5 GHz but they have lower breakdown voltages and therefore lower overall performance. The measured devices are double fingered with 0.8 mm total gate width.
Authors: Praneet Bhatnagar, Nicolas G. Wright, Alton B. Horsfall, Konstantin Vassilevski, C. Mark Johnson, Michael J. Uren, Keith P. Hilton, A.G. Munday, A.J. Hydes
Abstract: 4H-SiC depletion mode (normally-on) VJFETs were fabricated and characterised at temperatures up to 377 °C. The device current density at drain voltage of 50 V drops down from 54 A/cm2 at room temperature to around 42 A/cm2 at 377 °C which is a 20 % reduction in drain current density. This drop in drain currents is much lower than previously reported values of a 30 % drop in JFETs at high temperatures. The average temperature coefficient of the threshold voltage was found to be -1.36 mV/°C which is smaller than for most Si FETs. We have found that these devices have shown good I-V characteristics upto 377 °C along with being able to retain its characteristics on being retested at room temperature.

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