Three Dimensional Analysis of Turnoff Operation of SiC Buried Gate Static Induction Transistors (BG-SITs)

Koji Yano; Yasunori Tanaka; Tsutomu Yatsuo; Akio Takatsuka; Mitsuo Okamoto; Kazuo Arai

doi:10.4028/www.scientific.net/MSF.600-603.1075

Paper Titles

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Silicon Carbide Vertical JFET Operating at High Temperature
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Switching Performance of Epitaxially Grown Normally-Off 4H-SiC JFET
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1270V, 1.21mΩ·cm² SiC Buried Gate Static Induction Transistors (SiC-BGSITs)
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Three Dimensional Analysis of Turnoff Operation of SiC Buried Gate Static Induction Transistors (BG-SITs)
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Fabrication and Testing of 6H-SiC JFETs for Prolonged 500 °C Operation in Air Ambient
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Silicon Carbide Differential Amplifiers for High-Temperature Sensing
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SiC Lateral Trench JFET for Harsh-Environment Wireless Systems
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Development of High Temperature Lateral HV and LV JFETs in 4H-SiC
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HomeMaterials Science ForumMaterials Science Forum Vols. 600-603Three Dimensional Analysis of Turnoff Operation of...

Three Dimensional Analysis of Turnoff Operation of SiC Buried Gate Static Induction Transistors (BG-SITs)

Abstract:

The turnoff mechanism of SiC buried gate static induction transistors (SiC-BGSITs) were analyzed by three dimensional device simulation. A current crowding occurs in the portion near the channel center away from the gate contact during the initial phase of the turnoff operation, which is resulted from a non-uniform potential distribution through the gate finger with the displacement current flowing there. This increases the turnoff delay time. The impact of source length on the turnoff performance was made clear.