Materials Science Forum Vols. 527-529

Abstract: We performed solution growth of SiC single crystals from Si-Ti-C ternary solution using the accelerated crucible rotation technique (ACRT). It was confirmed that the growth rate exceeding 200 μm/hr was achievable by several ACRT conditions. This high growth rate might be due to the enhancement of the carbon transport from the graphite crucible to the growth interface using the ACRT. Moreover, the incorporation of inclusions of the Si-Ti solvent in the grown crystal was significantly suppressed by using the ACRT. It was thought that the intensive convection near the growth interface resulted in not only the marked increase of SiC growth rate but also the superior homogeneity in the surface morphology. It was concluded that faster stable growth can be accomplished in the SiC solution growth using the ACRT.

Abstract: Cubic-silicon carbide crystals have been grown from solution by using the traveling-zone method. In this technique a molten silicon zone heated by induction coils is held between two rods of polycrystalline silicon carbide. Due to the growth set-up and boundary conditions, different mass transfer mechanisms are operative : diffusion, buoyancy, Marangoni convection and forced convection. The growth experiments have been performed on various seed crystals. Cubic SiC crystals were grown with a [111] habit on the [0001] silicon faces of 4H SiC seeds. The polytype 3C-SiC was identified by Transmission Electron Microscopy. Micro Raman spectroscopy and photoluminescence analyses showed good crystalline quality with few 6H inclusions.

Abstract: From the engineering point of view, SiC hot-wall epitaxy is a very important process in SiC semiconductor processes. There are lots of experimental reports on SiC hot-wall epitaxy. They discussed the growth rate, surface morphology, doping concentration, etc. Recently, the effect of face polarity is also made clear. However, each report mentioned the particular results that strongly depend on the experimental conditions and reactor design. In addition, the discussion with inlet condition such as source gas C/Si ratio, not the depositing surface condition, leads to the confusion. In order to understand and try to design and optimize the hot-wall CVD reactor, a numerical approach is attempted. The authors have tried to make it clear that depositing surface condition might be a universal parameter of SiC CVD, and the numerical simulation could predict the growth rate, surface morphology and doping concentration by taking account of the depositing surface condition. In this study, at first, the recent progress of SiC hot-wall epitaxy in experiment is summarized. Then, the present status of its numerical modeling is explained.

Abstract: The rapid market development for SiC-devices during the last years can be attributed particularly to the success in supplying high-quality SiC wafers and corresponding epitaxial layers. The device quality could be enhanced and the costs were reduced by enlarging the wafer size as well as by a significant progress in epitaxial growth of active layers by using multi-wafer CVD systems. In this paper we want to give an overview of CVD multi-wafer systems used for SiC growth in the past and today. We present recent results of SiC homoepitaxial growth using our multi-wafer hot-wall CVD system. This equipment exhibits a capacity of 5×3” wafers per run and can be upgraded to a 7×3” or 5×4” setup. By optimizing the process conditions epitaxial layers with excellent crystal quality, purity and homogeneity of doping and thickness have been grown. Issues like reproducibility, drift of parameters and system stability over several runs will be discussed.

Abstract: Forward voltage instability, or Vf drift, has confounded high voltage SiC device makers for the last several years. The SiC community has recognized that the root cause of Vf drift in bipolar SiC devices is the expansion of basal plane dislocations (BPDs) into Shockley Stacking Faults (SFs) within device regions that experience conductivity modulation. In this presentation, we detail relatively simple procedures that reduce the density of Vf drift inducing BPDs in epilayers to <10 cm-2 and permit the fabrication of bipolar SiC devices with very good Vf stability. The first low BPD technique employs a selective etch of the substrate prior to epilayer growth to create a near on-axis surface where BPDs intersect the substrate surface. The second low BPD technique employs lithographic and dry etch patterning of the substrate prior to epilayer growth. Both processes impede the propagation of BPDs into epilayers by preferentially converting BPDs into threading edge dislocations (TEDs) during the initial stages of epilayer growth. With these techniques, we routinely achieve Vf stability yields of up to 90% in devices with active areas from 0.006 to 1 cm2, implying that the utility of the processes is not limited by device size.

Abstract: We have investigated the generation of new dislocations during the epitaxial growth of 4H-SiC layers. Dislocations were mainly propagated from the substrate into the epitaxial layer. However, it was found that some amount of new threading edge dislocations (TEDs) and basal plane dislocations (BPDs) were generated during the epitaxial growth. The generation of those dislocations appeared to depend on the in-situ H2 etching conditions, not the epitaxial growth conditions. By optimizing in-situ H2 etching condition, we were able to effectively suppress the generation of new dislocations during epitaxial growth, and obtain 4H-SiC epitaxial layers which have the equivalent etch pit density (EPD) to the substrates. Our additional investigation of the conversion of BPDs to TEDs revealed that its efficiency similarly depends on in-situ H2 etching. We were able to obtain a high conversion efficiency of 97 % by optimizing the in-situ H2 etching conditions before epitaxial growth.

Abstract: 4H-SiC epitaxial layers on Carbon-face (C-face) substrates were grown by a low-pressure hot-wall type chemical vapor deposition system. The C-face substrates were prepared by fine mechanical polishing using diamond abrasives with the grit size of 0.25 %m and in-situ HCl etching at 1400°C, which produced surface roughness of 0.27 nm. The use of the smooth substrates made it possible to decrease the substrate temperature and specular surface morphologies were realized at C/Si ratios of 1.5 or less both for a substrate temperature of 1550°C and for that of 1500°C. Surface roughness of 0.26 nm and the residual donor concentration of 6.7×1014 cm-3 were obtained for a C-face epitaxial layer grown at a C/Si ratio of 1.5 and at a substrate temperature of 1550°C. Schottky barrier diodes were fabricated on a non-doped C-face epitaxial layer grown at 1500°C and it was verified that a high quality metal-semiconductor interface was formed on the epitaxial layer.

Abstract: Experimental results are presented for SiC epitaxial layer growth employing a large-area, up to 8x100-mm, warm-wall planetary SiC-VPE reactor. This high-throughput reactor has been optimized for the growth of uniform 0.01 to 80-micron thick, specular, device-quality SiC epitaxial layers with low background doping concentrations of <1x1014 cm-3 and intentional p- and n-type doping from ~1x1015 cm-3 to >1x1019 cm-3. Intrawafer layer thickness and n-type doping uniformity (σ/mean) of ~2% and ~8% have been achieved to date in the 8x100-mm configuration. The total range of the average intrawafer thickness and doping within a run are approximately ±1% and ±6% respectively.

Abstract: The growth rate of 4H-SiC epi layers has been increased by a factor 3 (up to 18μm/h) with respect to the standard process with the introduction of HCl in the deposition chamber. The epitaxial layers grown with the addition of HCl have been characterized by electrical, optical and structural characterization methods. An optimized process without the addition of HCl is reported for comparison. The Schottky diodes, manufactured on the epitaxial layer grown with the addition of HCl at 1600 °C, have electrical characteristics comparable with the standard epitaxial process with the advantage of an epitaxial growth rate three times higher.

Abstract: The advantages of the CH3Cl carbon precursor were investigated in order to achieve good-quality homoepitaxial layers of the 4H-SiC polytype at temperatures lower than what was considered practical (or even possible) with C3H8-based growth. It was observed that the process window for good epilayer morphology becomes narrower when the growth temperature is decreased. Successful growth experiments have been conducted in this work down to a temperature of 1290-13000C, with the growth rate in excess of 2 +m/hr and a mirror-like defect-free epilayer surface morphology. Growth on a 2” substrate produced promising growth rate homogeneity. The dependence of the growth rate on SiH4 flow followed a clear exponential dependence. This trend is tentatively attributed to Si vapor condensation. Photoluminescence results suggest that the crystalline quality of the epilayers grown at 13000C is comparable to that of 17000C growth.