Abstract: This study examines how the increased density of passivated metallic conductor lines
caused by large circuit integration in semiconductor devices influence their reliability during a
thermal-cycling test. It was found that a decrease in the size of the trench-shaped space formed
between two passivated conductor lines reduces the thermal cycling reliability of the passivation
layer (i.e. in this case, consisting of Si3N4). The increased depth of the trenches results in more
severe deformation in the surrounding area and brittle fractures in the passivation layer. In particular,
the present work indicates that as the ratio of trench depth to trench width increases from 1:1 to 5:1,
the number of failures caused by thermal cycling increases up to 2-fold. Numerical calculation also
shows that the region of maximum stress is found at the corner of the interface between the flat
passivation layer (i.e., the surface without any trenches) and its underlying metallic conductor. In
cases where trenches exist, however, the region of maximum stress shifts from the interface corner
to the trench corner. Furthermore, the level of the maximum stress was calculated to be lower at the
interface corner than the trench corner, by 11%.
Abstract: The interfacial reactions and shear properties of Sn-37Pb (wt.%) solder bumps with two
different under bump metallizations (UBMs), Cu and Ni, were investigated after high temperature
storage (HTS) tests at 150 C for up to 65 days. Two different intermetallic compounds (IMCs),
Cu6Sn5 and Cu3Sn, were formed at the bump/Cu interface, whereas only a Ni3Sn4 IMC layer was
formed at the bump/Ni interface. The thicknesses of these IMCs increased linearly with the square
root of duration time. The IMC growth rate at the bump/Cu UBM interface was much greater than that
at the bump/Ni UBM interface. The shear properties of the bumps with the Cu UBM were greatly
decreased with increasing duration time, compared with those with the Ni UBM.
Abstract: In-situ observation by scanning electron microscope of the microstructure evolution near
the cathode depletion region and the quantitative analysis on the number of hillock phases in the
eutectic SnPb edge drift structure made it clear that the dominant migrating element and dominant
hillock phase were Sn and Pb, respectively, under 50 oC while both dominant migrating element and
dominant hillock phase were Pb above 100 oC. Such temperature-dependence of the dominant hillock
phases in the eutectic SnPb solder can be understood by considering the atomic size factors of the
metallic solid solutions.
Abstract: The structure and electrical properties of ZrO2 dielectric thin films deposited by rf
magnetron sputtering were investigated. The fixed oxide charge and interface trap density at the
ZrO2/Si interface is substantially decreased by annealing at 500 C. Annealing treatment also enhances
the quality of the film by reducing leakage current. The carrier transport mechanism in the ZrO2 film
is dominated by thermionic emission.
Abstract: Resistance-switching behaviors of the Pr0.7Ca0.3MnO3(PCMO) films based metalinsulator-
metal (MIM) devices has been investigated. In this work, resistance change of PCMO
films deposited with SRO buffer layers by using RF-magnetron sputtering system investigated at
room temperature. The ratio of the resistance change of the PCMO films with SRO buffer layers
in the high-resistance state to that in the low-resistance state turned out to be much lager than that
of the PCMO films without SRO buffer layers. Moreover, The reproducible property of the
fabricated samples were improved. Origin of resistance change is not clear, but PCMO films with
SRO buffer layers have the possibility of application for nonvolatile memory device.
Abstract: Ge2Sb2Te5 (GST) has been widely studied for PRAM as reversible phase change material.
GST is expected to reduce RESET (crystalline → amorphous) operation power, which is one of
important issues for PRAM technology. In order to investigate the effect of nitrogen doping on
electrical switching characteristics, we fabricated two kinds of PRAM cells with nitrogen-doped
(N-doped) and un-doped GST, which were different bottom electrode contact size (0.80~1.00 ).
N-doped GST PRAM cells have higher dynamic resistance with small sized bottom electrode contact
and lower RESET voltage (about 1.2 V, 50 ns) than un-doped GST PRAM cells (about 1.6 V, 50 ns).
The resistance switching ratio (RRESET to RSET) was about 100. The results of this study indicate that
nitrogen doping into GST film and smaller size of bottom electrode contact reduce RESET power for
Abstract: For flip-chip process of RF system-on-packages(SOP), double bump bonding processes
were investigated. Sn-Ag and Sn solder joints were formed by the reflowed double bumping process,
and Sn/In/Sn bump joints were fabricated by the non-reflowed double bump bonding process. The
height-to-size ratios of 0.78 and 0.65 were obtained for the reflowed double bumping and the
non-reflowed bumping, respectively. Average contact resistance of the reflowed Sn-Ag and Sn solder
joints was about 13m/ which was much lower than 24~33m/ of the non-reflowed Sn/In/Sn bump joints.
The reflowed solder double bumping method is more suitable for flip-chip process of RF-SOP than the
non-reflowed double bump bonding.
Abstract: The ambient and denuded trench top corner at the step of gate oxidation play an important
role to generate defect. Furthermore, dislocation-free flash process is proposed, and its mechanism as
well. The impact on dislocation of the other processes is also discussed. And we knew that using of
dry oxidation for gate oxide has the characteristic to reduce the dislocation. Consequently, the
dislocation free wafer is obtained by changing gate oxide from wet to dry in manufacturing embedded