Materials Science Forum Vols. 483-485

Abstract: This paper presents new observations resulting from in-situ high temperature hydrogen etching of 4H-SiC mesas that were step-free prior to initiation of etching. In particular, it was found that well-ordered pyramidal-shaped step train structures could be produced on mesa top surfaces via stepflow etching proceeding inward from the sides of mesas. In many cases, the height of steps etched inward from {112 0} mesa sides is 0.5 nm (2 Si-C bilayers), while the height of steps etched inward from {11 00} sides of the same mesa is 1.0 nm (4 Si-C bilayers, the repeat distance of the 4H-SiC polytype). We propose that stepflow etching starting from the mesa sidewall and involving step-to-step repulsive forces produces the observed step train structures.

Abstract: We study for the effects of additional gas such as oxygen (O2) and hydrogen (H2) into SF6. When H2 gas was added to SF6, surface fluoride atomic concentration and surface roughness were lower than the other additional gases. Surface fluoride atomic concentration under this experiment was reduced from 28 at % to 6 at % by the H2 addition. In post-processing, the fluoride atomic concentration was succeeded in a large reduction by processing H2, O2 plasma and high temperature hydrogen annealing. In hydrogen annealing, surface fluoride atomic concentration could be suppressed to less than 3 at %. This is new result succeeded in reduction of surface fluoride species greatly by hydrogen processing.

Abstract: Commercial on-axis wafers of 4H-SiC(0001) were etched in a standard reactor for chemical vapor deposition (CVD) using molecular hydrogen flux in order to improve the structure and morphology of the surface. The substrate temperature during etching was varied from 1400 to 1600°C. Characterization of the surface morphology was performed using optical and atomic force microscopy (AFM). Low-energy electron diffraction (LEED) and X-ray photoelectron spectroscopy (XPS) were also used to examine the surface structure and chemical composition of the samples. The sample of best quality was obtained for an etching temperature of 1400°C. Its surface is ° × 30 ) 3 3 ( R reconstructed and covered by an ordered “silicate” layer. Increasing the substrate temperature during etching to 1500°C leads to enhanced step-bunching and the formation of macroterraces. At 1600°C distinct depressions appear on the surface, presumably from etching of structural defects such as screw dislocations. Subsequent annealing at 1000°C in ultra-high vacuum (UHV) removes the surface oxide and produces the ° × 30 ) 3 3 ( R surface phase of clean 4HSiC( 0001).

Abstract: Reactive ion etching of SiC induced surface damage, e.g., micromasking effect induced coarse and textured surface, is one of the main concerns in the fabrication of SiC based power devices [1]. Based on CHF3 + O2 plasma, 4H-SiC was etched under a wide range of RF power. Extreme coarse and textured etched surfaces were observed under certain etching conditions. A super-linear relationship was found between the surface roughness and RF power when the latter was varied from 40 to 160 W. A further increase in the RF power to 200 W caused the surface roughness to drop abruptly from its maximum value of 182.4 nm to its minimum value of 1.3 nm. Auger electron spectroscopy (AES) results revealed that besides the Al micromasking effect, the carbon residue that formed a carbon-rich layer, could also play a significant role in affecting the surface roughness. Based on the AES results, an alternative explanation on the origin of the coarse surface is proposed.

Abstract: This paper presents much more details on the process of etching n and p type SiC using a dc saddle field source. Here is described a method for stabilizing the dc discharge by adding controlled flow of O2 to SF6 in the source chamber. This kind of etching is used to fabricate 4H-SiC p-i-n diodes with a junction periphery protection. The effect of the junction periphery protection, the source power that terminates the etching process and testing environment on the breakdown voltage are investigated. The optimised p-i-n diodes exhibit a stable reverse bias operation with a breakdown voltage of 1700 V.

Abstract: The defects were investigated in p+nn+ 4H-SiC diodes by observing the forward-biasinduced light emission through the substrate. The spatial intensity distribution, the temporal evolution and the spectral content of the electroluminescence (EL) signal have been measured in order to detect, identify and understand the defect formation during forward-bias application. It was found that, exept from the dislocations inside the epilayers, mesa etching is a main cause for the formation of extended defects. To our knowledge, for the first time, reduction of mesa-etchinginduced defects is shown in this investigation.

Abstract: The effects of the damage induced during ion implantation on the surface roughening and oxide growth rate were investigated. Using several scheme of doses and acceleration energies, it is found that the amount of the dose predominantly produce damage rather than the acceleration energy, especially near the surface region. It was also found that the damage affects not only the oxide growth rate but also the surface roughening during high temperature annealing. The edge of highly implanted area may have higher doping concentration due to the vicinal side wall effect of the thick oxide mask for ion implantation. It was confirmed by the trench formation after thermal oxide remove.

Abstract: QuaSiC TM substrates can be obtained by transferring a single crystal SiC layer onto a poly SiC substrate using the Smart Cut TM technology. The structure evolution of metal bonding (W-Si silicide) layer has been investigated by Transmission Electron Microscopy and X-ray diffraction. Results indicate that the metal bonding film is made of W5Si3. The film is discontinuous and strained. Annealing releases stress at least partially.

Abstract: The challenges of packaging SiC power devices for high temperatures include high operating temperature, wide thermal cycle range, high currents and high voltages. This paper describes ongoing research to develop suitable materials and processes for packaging SiC power devices. Ohmic and Schottky contacts must be protected from oxidation at elevated temperatures. TaSi2:N2 is an effective oxidation barrier, protecting the contacts when exposed to 350 oC in air. For package substrates, silicon nitride ceramics with a thick brazed copper foil are used. A nickel/thick gold or nickel/thick silver surface finish is plated onto the copper foil; depending on the die attach brazing process. With the nickel/thick gold finish, gold-tin eutectic has demonstrated no degradation in die shear strength after 2000 hours at 350 oC or after 500 hours at 400 oC. Work is currently underway with nickel/thick silver and gold-silicon eutectic die attach. No degradation in shear strength has been observed with this system after 100 hours at 400 oC. Gold wire (250 µm) bonding has been demonstrated on both substrate and SiC metallizations. An initial decrease in strength is observed due to annealing of the gold wire, but shear and pull strengths remain high. Polyimide has been used to increase the dc breakdown strength of a test pattern by a factor of ~3x at 300 oC compared to no passivation. The breakdown strength increased with storage in air at 300 oC through 1000 hours.

Abstract: We report the simulation results of 25µm half cell pitch vertical type 4H-SiC DiMOSFET using the general-purpose device simulator MINIMOS-NT. The best trade-off between breakdown voltage and on-resistance in terms of BFOM is around 19MW/cm2 with a p-well spacing 5µm. The specific on -resistance, RON, sp, simulated with VGS=10V and VDS=1V at room temperature, is around 22.76mWcm2. An 900V breakdown voltage is simulated with ion-implanted edge termination.