Materials Science Forum Vols. 483-485

Abstract: Al-Si patterns were formed on n-type 4H-SiC substrate by a photolithographic process including wet Al etching and Si/SiC reactive ion etching (RIE) process. RF 1000°C annealing under C3H8 flow was performed to obtain p+ SiC layers by a Vapour-Liquid-Solid (VLS) process. This method enables to grow layers with different width (up to 800 µm) and various shapes. Nevertheless the remaining Al-based droplets on the largest patterns are indicators of crack defects, going through the p+ layer down to the substrate. SIMS analyses have shown an Al profile with high doping concentration near the surface, high N compensation and Si/C stoechiometry variation between the substrate and the VLS layer. The hydrogen profile follows the Al profile in the VLS layer with an overshoot at the VLS/substrate interface. I-V measurements performed directly on the semiconductor layers have confirmed the formed p-n junction and allowed to measure a sheet resistance of 5.5 kW/ı

Abstract: 500 keV nitrogen implantations at different tilt angles (0o, 0.5o, 1.2o, 1.6o, 4o) with respect to the c-axis of 6H-SiC were carried out. Radiation damage distributions have been investigated by Backscattering Spectrometry combined with channeling technique (BS/C) using 3550 keV 4He+ ion beam. A comparative simultaneous evaluation of the damage depth distributions in the Si and C sublattices of 6H-SiC led to a correction factor of 0.8 in the electronic stopping power of 4He+ ions along <0001> channel. Full-cascade Crystal-TRIM simulations with the same set of damage accumulation model parameters could reconstruct the measured shapes and heights of damage distributions for all implantation tilt angles. Secondary defect generation effects in addition to the primary point defect accumulation were assumed in the analysis.

Abstract: Hall effect investigations taken on Si+-/N+-, C+-/N+- or Ne+-/N+-co-implanted 4H-SiC layers and deep level transient spectroscopy investigations taken on Si+-implanted 4H-SiC layers provide experimental evidence for an electrically neutral defect complex formed during the annealing process at temperatures between 1400°C and 1700°C. This defect complex consumes nitrogen donors and an intrinsic Si containing defect species (interstitial Si or Si-antisite) or Cvacancies. At our present knowledge, we favor an (NX-SiY)-complex.

Abstract: We report a full wafer scale investigation of the activation of nitrogen and phosphorus ions co-implanted at room temperature in a 4H-SiC semi-insulating wafer. We used a full 35 mm wafers on which, after implantation and annealing, 77 reticules with Hall bars and TLM motifs were processed. We found an average sheet resistance of 531 W/square with 30 W/square standard deviation.

Abstract: n+/p diodes have been realized by 300°C phosphorus ion implantation and subsequent annealing at 1300°C. An electrical characterization of the devices as well as a study of the defects introduced by the implantation process has been made. I-V measurements pointed out that the diodes maintain a good rectifying behavior up to 737K. DLTS analyses detected the presence of three traps, T2, T3 and T4, which are not due to the implantation process, and a high energy trap, T5, that could be related to the surface states at the Ni/SiC interface.

Abstract: In this work, we present results on the study of bonding and concentration of carbon in 4H-SiC MOS structure by x-ray photoelectron spectroscopy (XPS). The XPS spectra were fitted by several Gaussian lineshape functions. It is found that the so-called carbon clusters (C-C bonds) appear at the interface of SiO2/SiC, but are not seen in the oxide bulk. However, there are still some SiOxCy and Si-C bonds inside the oxide and the integrated area ratio of SiOxCy/Si-C bonds increases when further away from the SiO2/SiC interface. These observations can be interpreted in terms of the dynamic oxidation process that transforms Si-C bonds into SiOxCy bonds, which are then further oxidized to form SiO2 bonds.

Abstract: The mechanisms of oxygen incorporation during dry thermal oxidation of 6H-SiC wafers were investigated. Isotopic tracing of oxygen was performed by sequential oxidations in dry O2 enriched or not in the 18O isotope and subsequent determinations of the 18O profiles. The results obtained with SiC substrates were compared with those of Si, evidencing different mechanisms of oxygen incorporation and transport. The gradual nature of the SiO2/SiC interface was also evidenced. A probable explanation for this gradual SiO2/SiC interface is shown to be the formation of C clusters during oxidation.

Abstract: The effects of dislocations in n-type 4H-SiC(0001) epitaxial wafers on the reliability of thermal oxides have been investigated. Charge-to-breakdown (QBD) values of thermal oxides decrease with increase in the dislocations under a gate-oxide area. Nomarski microscope observations show that dielectric breakdown of thermal oxides occurs at the position of dislocation in epitaxial layer. It is reavealed that basal plane dislocation is the most common cause of the dielectric breakdown.

Abstract: The wet oxidation of (0001), Si-face, 6H-SiC pre-amorphised by Ar+ implantation has been investigated in the temperature range between 750 and 950 °C. Electron microscopy analysis has been performed to obtain information on the evolution of the amorphous layer during the oxidation process. When the oxidation occurs on the amorphous substrate the observed rate is given by VOx(a)=3.8x107exp(-1.6eV/kT) nm/min, by far faster than that observed on single or polycrystalline 6H-SiC. For amorphous layer thickness of a few hundreds nanometer and processing time of a few tens of minutes this happens up to oxidation temperatures of about 910 °C, owing to the concomitant recrystallization process. At higher temperature, our oxidation data support the existence of a sudden variation of the recrystallization process that rapidly reduces the residual amorphous region and, consequently, the oxide thickness. However, it appears that this second recrystallization stage is faster than previously estimated. Structural detail of the starting amorphous-crystalline interface and of the early-recrystallized layers are reported and discussed.

Abstract: A high temperature rapid thermal processing (HT-RTP) above 1400oC was investigated for use in the gate oxide formation of 4H-SiC by a cold-wall oxidation furnace. The gate oxide film of ~50nm can be formed for several minutes in the oxidizing atmospheres such as N2O and O2, where the oxidation rates were 8-10nm/min. After the initial oxide formation, the HT-RTPs in various ambient gases were conducted, and the dependences of their MOS interface properties on the gases were evaluated by a capacitance-voltage (CV) measurement. Based on the results, the process sequence of gate oxidation was determined as follows; the initial oxide was formed by the HT-RTO (oxidation) in N2O or in O2 with subsequent post annealing in Ar ambient, and then the HT-RTN (nitridation) in NO was conducted. The total process time becomes 20-50min. The interface trap density (Dit) of fabricated MOS capacitor shows 3-5x1011cm-2eV-1 at Ec-E~0.2eV. The field-effect channel mobility of fabricated 4H-SiC lateral MOSFETs was ~30cm2/Vs.