Silicon Carbide and Related Materials 2004

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Authors: Amador Pérez-Tomás, Dominique Tournier, Phillippe Godignon, Narcis Mestres, José Millan
Abstract: Thin (~10nm) Si layers have been deposited using Rapid Thermal CVD at temperatures ranging 950°C-1050°C. RTCVD deposited Si layers have been oxidized using N2O at 1300°C during relatively short times (15min) to produce SiO2 layers of 20-30nm. The interfacial characteristics of N2O oxidized RTCVD layers have been studied using the conductance method, showing a reduced traps density and a low band bending fluctuation when compared with conventional N2O grown oxides on 4H-SiC substrates. The surface topology of these layers has also been analyzed evidencing an adequate topography with low roughness.
673
Authors: Satoshi Tanimoto, Hideaki Tanaka, Tetsuya Hayashi, Yoshio Shimoida, Masakatsu Hoshi, Teruyoshi Mihara
Abstract: Thin (~10nm) Si layers have been deposited using Rapid Thermal CVD at temperatures ranging 950°C-1050°C. RTCVD deposited Si layers have been oxidized using N2O at 1300°C during relatively short times (15min) to produce SiO2 layers of 20-30nm. The interfacial characteristics of N2O oxidized RTCVD layers have been studied using the conductance method, showing a reduced traps density and a low band bending fluctuation when compared with conventional N2O grown oxides on 4H-SiC substrates. The surface topology of these layers has also been analyzed evidencing an adequate topography with low roughness.
677
Authors: Kumaresan Ramanujam, Hidetsugu Furuichi, Koshi Taguchi, Satoshi Yukumoto, Shigehiro Nishino
Abstract: Investigations were carried out to achieve high performance Silicon Carbide Metal-Oxide-Semiconductor device structures. 4H-SiC/SiO2 interface was prepared by growing amorphous SiO2 layers by an alternate low temperature atmospheric CVD technique using TEOS as source material and the interface properties were compared with the one prepared by conventional thermal oxidation technique. The low temperature CVD technique offered the improvement of the interface properties with reduced Dit in comparison with thermally oxidized interface. As a new attempt, an in situ post growth annealing technique in N2 atmosphere was carried out to reduce the Dit further. Both the CVD technique and the in situ annealing processes that were used in the present study have been identified to be potential approaches to improve the interface quality.
681
Authors: Hiroshi Yano, Tomoaki Hatayama, Yukiharu Uraoka, Takashi Fuyuki
Abstract: High temperature (1250 oC) NO annealing was performed for deposited oxide (SiO2) and oxynitride (SiON) films on n-type 4H-SiC. Interface state density of SiO2 samples was dramatically reduced (one order of magnitude) by NO annealing compared to N2 annealing, resulting in 1x1011 cm-2eV-1 at 0.2 eV below the conduction band edge. In contrast, that of NO annealed SiON samples showed only 30% decrease and was still in the range of 1x1012 cm-2eV-1. These different effects of NO annealing against SiO2 and SiON are probably due to different reaction mechanism at the interface. Breakdown field of SiO2 samples annealed in NO was as high as 10 MV/cm. Barrier height of this sample was 2.86eV, which is close to the ideal value.
685
Authors: K.Y. Cheong, Wook Bahng, Nam Kyun Kim
Abstract: In this paper, the electrical properties of pre- and post-rapid thermal annealed 4H SiC-based gate oxide grown in 10% nitrous oxide (N2O) and in dry oxygen have been investigated, compared, and reported for the first time. After treating the nitrided gate oxide in rapid thermal annealing (RTA), oxide breakdown characteristic has been improved significantly. This improvement has been attributed to the reduction of SiC–SiO2 interface-trap density and the generation of positive oxide charge, acting as an electron-trapping center. However, deleterious effects have been observed in non-nitrided oxide after subjected to the same RTA treatment. The differences in oxide-breakdown strength of these oxides have been explained and modeled.
689
Authors: Florin Ciobanu, Gerhard Pensl, Valeri V. Afanas'ev, Adolf Schöner
Abstract: A surface-near Gaussian nitrogen (N) profile is implanted into n-type 4H-SiC epilayers prior to a standard oxidation process. Depending on the depth of the oxidized layer and on the implanted N concentration, the density of interface states DIT determined in corresponding 4H-SiC MOS capacitors decreases to a minimum value of approx. 1010 cm-2eV-1 in the investigated energy range (EC-(0.1 eV to 0.6 eV)), while the flat-band voltage increases to negative values due to generated fixed positive charges. A thin surface-near layer, which is highly N-doped during the chemical vapour deposition growth, leads to a reduction of DIT only close to the conduction band edge.
693
Authors: Keiko Fujihira, Yoichiro Tarui, Kenichi Ohtsuka, Masayuki Imaizumi, Tetsuya Takami
Abstract: The effect of N2O anneal on channel mobility of inversion-type 4H-SiC n-channel MOSFET has been systematically investigated. It is found that the mobility increases with increasing anneal temperature from 900 to 1150°C. The highest field effect mobility of 30 cm2/Vs is achieved by 1150°C anneal for 3 h, which is about 20 times higher than that for non-annealed MOSFET. In order to investigate the oxide reliability, TDDB measurement has been performed on SiO2 grown on n-type 4H-SiC. The oxide lifetime is found to be drastically improved by N2O anneal.
697
Authors: Maciej Wolborski, Mietek Bakowski, Viljami Pore, Mikko Ritala, Markku Leskelä, Adolf Schöner, Anders Hallén
Abstract: Aluminium oxide and titanium oxide films were deposited using the Atomic Layer Deposition method on n-type 4H SiC and p-type Si {001} substrates, with doping 6×1015cm-3 and 2×1016cm-3, respectively, and on 1.2 kV PiN 4H SiC diodes for passivation studies. The Al2O3 and SiC interface was characterised for the existence of an effective negative charge with a density of 1×1012-2×1012 cm-2. The dielectric constant of Al2O3 as determined from capacitance-voltage data was about 8.3. The maximum electric field supported by the Al2O3 film was up to 7.5 MV/cm and 8.4 MV/cm on SiC and Si, respectively.
701
Authors: Marc Avice, Ulrike Grossner, Edouard V. Monakhov, Joachim Grillenberger, Ola Nilsen, Helmer Fjellvåg, Bengt Gunnar Svensson
Abstract: In this study, electrical properties of Al2O3 deposited by Atomic Layer Deposition (ALCVD) on n-type 4H-SiC were investigated. Metal-Oxide-Semiconductor (MOS) capacitors were characterized by various electrical techniques such as Capacitance-Voltage (CV), Current- Voltage (IV) and Deep Level Transient Spectroscopy (DLTS) measurements. Two different oxidants, H2O and O3, have been used for the oxide deposition. After deposition, the flat-band voltage shift is much less using O3 than H2O (~ 7V versus ~ 20V). Annealing treatment has been carried out at different temperatures in Ar atmosphere up to 700°C. Whereas the flat-band voltage shift can be reduced by annealing, the leakage current remains rather high.
705
Authors: A. Paskaleva, R.R Ciechonski, Mikael Syväjärvi, E. Atanassova, Rositza Yakimova
Abstract: The electrical properties of Al2O3 as a gate dielectric in MOS structures based on n- and p-type 4H-SiC grown by sublimation method have been investigated and compared to the properties of similar structures utilizing SiO2. The electrically active defects in the structures are studied by CV method. The results show that the type as well as spatial and energy distribution of defects in Al2O3/SiC and SiO2/SiC samples are different. The structures with Al2O3 on p-type 4H-SiC demonstrate much better C-V characteristics than the p-type 4H-SiC/SiO2 structures.
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