Materials Science Forum Vols. 483-485

Abstract: Due to the high critical field in 4H-SiC, the drain charge and switching loss densities in a SiC power device are approximately 10X higher than that of a silicon device. However, for the same voltage and resistance ratings, the device area is much smaller for the 4H-SiC device. Therefore, the total drain charge and switching losses are much lower for the 4H-SiC power device. A 2.3 kV, 13.5 mW-cm2 4H-SiC power DMOSFET with a device area of 2.1 mm x 2.1 mm has been demonstrated. The device showed a stable avalanche at a drain bias of 2.3 kV, and an on-current of 5 A with a VGS of 20 V and a VDS of 2.6 V. Approximately an order of magnitude lower parasitic capacitance values, as compared to those of commercially available silicon power MOSFETs, were measured for the 4H-SiC power DMOSFET. This suggests that the 4H-SiC DMOSFET can provide an order of magnitude improvement in switching performance in high speed switching applications.

Abstract: Lateral MOSFET devices with varying size from a single unit cell to 3x3 mm2 containing 1980 unit cells have been realised using two basic technologies; lateral trench MOSFET (LTMOS) with epitaxially grown source and drain, and lateral MOSFET with lightly doped drain (LDDMOS) having implanted source and drain regions. The LDDMOS devices had blocking capability of 100 V and the channel mobility in the range of 10 cm2/Vs in {-110} current flow direction and of 5 cm2/Vs in {110} current flow direction. The properties of both fabricated MOSFET types, LTMOS and LDDMOS, are dominated by a high density of interface states of the order of 1×1013 cm-2eV-1. Both the drain current and the leakage current scale linearly with the device size up to the maximum investigated device size of 3x3 mm2. No size limiting defects have been observed contrary to what is often the case in 4H-SiC material.

Abstract: We have fabricated lateral RESURF MOSFETs on 4H-SiC(0001) Si-face and (000-1) C-face substrates, and compared those properties. The channel mobility of a lateral test MOSFET on a C-face was 41 cm2/Vs, which was much higher than 5 cm2/Vs for that on a Si-face. The specific on-resistance of the lateral RESURF MOSFET on a C-face was improved to 79 mΩcm2 as comparison with 2400 mΩcm2 for Si-face. The breakdown voltage was 490V for Si-face and 460V for C-face, which was 82% and 79% of the designed breakdown voltage of 600V, respectively. The device breakdown occurred destructively at the gate electrode edge.

Abstract: Optimum dose designing for 4H-SiC (0001) two-zone RESURF MOSFETs is investigated by device simulation and fabrication. Simulated results suggest that negative charge at the SiC/SiO2 interface significantly influences breakdown voltage. Simulation has also showed that breakdown voltage strongly depends on LDD (Lightly-Doped Drain) dose. The dose dependencies of the breakdown voltage experimentally obtained are in good agreement with the device simulation. A RESURF MOSFET, processed by N2O oxidation, with an optimized dose blocks 1080V and has a low on-resistance of 79 mcm2 at a gate oxide field of 3.0 MV/cm, which is the best 4H-SiC RESURF MOSFET ever reported.

Abstract: In our previous study, the on-resistance of the SiC-based vertical MOSFET had been reduced in double-epitaxial MOSFET (DEMOSFET). The device exhibited an on-resistance (Rons) of 8.5 mWcm2 with a blocking voltage (Vbr) of 600 V. This study analyzed the characteristics of the DEMOSFET using a numerical simulation. The results showed the trade-off relationship between the specific on-resistance and the blocking characteristics when the concentration of the nitrogen ions increases in the surface of the n-type region between the p-wells. Specially, the specific on-resistance was drastically improved by increasing the concentration of the nitrogen ions. The thick gate oxide on the n-type region between the p-wells had an advantage to suppress the electric field in the gate oxide.

Abstract: In our previous paper [1], we simulated an accumulation-mode MOSFET with an epitaxial layer channel (epi-channel) that had a high channel mobility. In this paper, we experimentally show that channel mobility is enhanced by the epi-channel. On varying the thickness of the epi-channel, the channel mobility improved from a few cm2/Vs to 100 cm2/Vs. Finally, we show that the “Normally-off” accumulation MOSFET with a 720 V breakdown voltage has a low on-resistance (10.4 m1cm2) and that the 3 × 3 mm2 accumulation MOSFET operates over 10 A and its on-resistance is 19 m1cm2.

Abstract: Short-channel effects in SiC MOSFETs have been investigated. Planar MOSFETs with various channel lengths have been fabricated on p-type 4H-SiC (0001), (000-1) and (11-20) faces.^Short-channel effects such as punchthrough behavior, decrease of threshold voltage and deterioration of subthreshold characteristics are observed. Furthermore, the critical channel lengths below which short-channel effects occur are analyzed as a function of p-body doping and oxide thickness by using device simulation. The critical channel lengths in the fabricated SiC MOSFETs are in agreement with those obtained from the device simulation. The results are also in agreement with the empirical relationship for Si MOSFETs.

Abstract: The behavior of the MOS switch and of two cascode configurations are evaluated, by using OR-CAD simulations, and the resulting data are comparatively presented. By analytical and numerical investigations, the superior performance of the multiple cascode circuit is demonstrated.

Abstract: This paper reports on the degradation of inversion channel mobility of SiC MOSFET caused by the increase of channel doping. SiC MOSFETs were fabricated on three wafers, the doping concentrations of the epitaxial layer of which were 16 10 2× cm-3 (sample A), 17 10 2× cm-3 (sample B) and 17 10 4× cm-3 (sample C). The field effect mobility sharply decreases as the doping concentration increases. Hall mobility measurements have been done to investigate the degradation of the mobility due to doping. The measurement of sample A shows that, as a consequence of the decrease of the free carrier density due to MOS interface traps, the Hall mobility is as much as a factor of ten higher than the field effect mobility. In contrast, in regard to the measurement of sample B and sample C, we encountered unstable Hall voltage and could not obtain reproducible results. This implies that such high-density traps are generated that a channel disappears in the higher-doping samples.

Abstract: We report investigations of Si face 4H-SiC MOSFETs with aluminum ion implanted gate channels. High quality SiO2/SiC interface is obtained both when the gate oxide is grown on p-type epitaxial material and when grown on ion implanted regions. A peak field effect mobility of 170 cm2/Vs is extracted from transistors with epitaxially grown channel region of doping 5x1015 cm-3. Transistors with implanted gate channels with aluminum concentration of 1x1017 cm-3 exhibit peak field effect mobility of 108 cm2/Vs, while the mobility is 62 cm2/Vs for aluminum concentration of 5x1017 cm-3. The mobility reduction with increasing acceptor density follows the same functional relationship as in n-channel Si MOSFETs.