Abstract: We report on the study of the p-type doping of 4H-SiC material using
HexaMethylDiSilane/TriMethylAluminium/Propane (HMDS/TMA/P) system in place of the usual Silane/TriMethylAluminium/Propane (S/TMA/P) precursors. The influence of growth parameters such as TMA flow, growth rate or C/Si ratio is investigated. The aluminium incorporation level is deduced from both by C(V) (mercury probe) and SIMS measurements. The presence of aluminium in the layers is confirmed by non-destructive optical micro-Raman experiments. Good quality p-type, aluminium doped 4H-SiC layers can be grown using
HMDS/TMA/P system. The amount of aluminium in the layers can be controlled by choosing the growth conditions and an aluminium concentration as high as 2x1019 at.cm-3 has been reached.Finally, comparing the two HMDS/TMA/P and S/TMA/P systems, no difference in aluminium incorporation has been found.
Abstract: The so-called VLS (Vapour-Liquid-Solid) mechanism in an Al-Si melt has recently
demonstrated the capability to grow at low temperature single crystalline 4H-SiC layers, with a high Al content. Using the newly developed VLS technique, we have deposited several 4H-SiC layers and determined the incorporated Al level by SIMS (Secondary Ion Mass Spectroscopy). Depending on the sample, we have found that the SIMS doping level ranges from 5x1019 to 1x1021 at.cm-3. This last value is the highest one reported so far for in-situ doped SiC:Al. From TEM (Transmission
Electron Microscopy) analyses we show that the layers are single crystals, with a high density of defects located only at the lower interface and no foreign phase inclusion. These results compare well with the ones obtained in previous works using alternative doping techniques, like ion implantation, chemical vapour deposition or sublimation. It thus suggests that Al solubility limit in SiC is rather temperature independent.
Abstract: For preliminary step toward fabrication of MOSFET using 4H-SiC 8) 3 (03 prepared by sublimation method, epitaxial growth of device quality 4H-SiC on 4H-SiC (0001) 8.0° off substrate was carried out and investigated. Smooth and specular surface of 4H-SiC (0001) plane was obtained by optimum growth condition. And epitaxial growth on 4H-SiC 8) 3 (03 and ) 8 3 (03 substrates were carried out with optimum growth conditions of 4H-SiC (0001). Smooth and specular surface was obtained on 4H-SiC 8) 3 (03 and ) 8 3 (03 plane. Growth rate of epilayers of 4H-SiC (0001), 8) 3 (03 and ) 8 3 (03 face were same. Oxidation rate of 4H-SiC (0001), ) 1 (000 , 8) 3 (03 and ) 8 3 (03 face was investigated. The oxidation rate was different depending on the faces. It was observed that the difference of oxidation rate of 8) 3 (03 and ) 8 3 (03 is mainly due to the difference of polarity similar to the case of reported for (0001) and ) 1 (000 .
Abstract: Epitaxial growth of 4H-SiC has been carried out at temperatures up to 1650 oC on 4HSiC substrates dipped in strongly diluted Si-based solutions. Liquid Phase Epitaxy (LPE) in conditions of low supersaturation was shown to be an effective technique to overgrow micropipe defects (MPs) in SiC wafers prepared by the Physical Vapour Transport (PVT) technique. The aim of this work was to investigate the SiC growth morphology and the dependence of MP elimination
efficiency on Si-Ge flux composition. Macroscopically flat, single crystalline SiC layers of a thickness up to 10 µm were grown with a growth rate of about 0.5 µm/h. Stepped growth morphology was observed independent of the melt composition. Micropipes with the diameter below 5 µm were closed with an efficiency of about 80%. SEM investigations as well as inspection under reflected/transmitted light did not show any specific distortion of the growth morphology at the micropipe healing place.
Abstract: Experimental results are presented for SiC epitaxial layer growths employing a largearea, 7x3-inch, warm-wall planetary SiC-VPE reactor. This high-throughput reactor has been optimized for the growth of uniform 0.01 to 30-micron thick, specular, device-quality SiC epitaxial layers with background doping concentrations of <1x1014 cm-3. Multi-layer device profiles such as Schottky, MESFETs, SITs, and BJTs with n-type doping from ~1x1015 cm-3 to >1x1019 cm-3, p-type
doping from ~3x1015 cm-3 to >1x1020 cm-3, and abrupt doping transitions (~1 decade/nm) are regularly grown in continuous growth runs. Intrawafer layer thickness and n-type doping uniformities of <1% and <5% s/mean have been achieved. Within a run, wafer-to-wafer thickness and doping variation are ~±1% and ~±5% respectively. Long term run-to-run variations while under process control are approximately ~3% s/mean for thickness and ~5% s/mean for doping.
Latest results from an even larger 6x4-inch (100-mm) reactor are also presented.
Abstract: In this paper we present recent results of epitaxial growth of 4H-SiC on 3” (0001) 8° and 4° off-oriented wafers using a multi-wafer hot-wall CVD system. This equipment exhibits a capacity of 5x3” or 7x2” wafers per run. By optimizing the process conditions epitaxial layers with excellent crystal quality, purity and homogeneity in doping and thickness were grown. The intra-wafer as
well as the wafer-to-wafer homogeneity will be illustrated by doping and thickness mappings of a full-loaded run. Surface morphology of epitaxial layers on 8° and 4° off-oriented wafers was investigated by atomic force microscopy.
Abstract: The epitaxial overgrowth process was examined with a view to realizing the
p-buried floating junction structure. The growth condition was investigated to reduce the p-type impurity contamination and to minimize the auto-doping. Total p-type impurity concentration was reduced to 1/50 of the n-type carrier concentration of the drift layers. The buried p-type floating structure was realized for the first time, using 4H-SiC material.
Abstract: Generation of stacking faults (SFs) in fast epitaxial growth of 4H-SiC(0001) has been reduced in vertical hot-wall chemical vapor deposition (CVD). 52 µm-thick epilayers with and without SFs are used to investigate impacts of SFs on the performance of Schottky barrier diodes (SBDs). The density, shape and structure of stacking faults have been characterized by cathodeluminescence (CL), photoluminescence (PL) and high-resolution transmission electron
microscopy (HR-TEM). These analyses indicate that most (> 75 %) SFs with an 8H structure are generated near the epilayer/substrate interface during CVD. It is also revealed that the SFs cause the lowering of Schottky barrier height as well as the decrease of breakdown voltage.
Abstract: We present a survey of the most important factors relating to an epitaxial SiC growth
process that is suitable for bipolar power devices. During the last several years, we have advanced our hot-wall SiC epitaxial growth technology to the point that we can support the transition of bipolar power devices from demonstrations to applications. Two major concerns in developing a suitable epitaxial technology are epilayer uniformity and extended defect density. Our state-of-theart capability permits the realization of 1-cm2 area devices with exceptional yields. Another major
concern is the stability of bipolar devices during forward conduction. We have developed proprietary substrate and epilayer preparation technologies that have essentially eliminated Vf drift as a significant barrier to the exploitation of SiC based bipolar devices.
Abstract: Selective nitrogen doping of 4H-SiC by epitaxial growth using TaC as the high
temperature mask has been demonstrated. Nomarski optical microscope and scanning electron microscope (SEM) were used to characterize selective growth of SiC. In addition, 250µm square shaped p-n junction diodes by selective n type epitaxial growth on p type epi layer were fabricated. The refilled fingers with different width were designed to vary the periphery/area (P/A) ratio. The effects of P/A ratio on the current-voltage (J-V) characteristics have been investigated. The ideality factor extracted from J-V characteristics is ≈2 at temperature range of 25-275°C, which indicates that the Shockley-Read-Hall recombination is the dominant mechanism in the conduction region. The reverse leakage current did not show dependence on P/A ratio for trench refilled diodes. The room temperature reverse leakage current density at 100V is less than 3.5×10-7 A/cm2 for all diodes. Also, the reverse leakage current did not increase significantly with temperature up to 275°C. The breakdown voltages measured at room temperature are about 450V and 400V for diodes without and with fingers, respectively.