Defect Control in Growth and Processing of 4H-SiC for Power Device Applications

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Extended defects and deep levels generated during epitaxial growth of 4H-SiC and device processing have been reviewed. Three types in-grown stacking faults, (6,2), (5,3), and (4,4) structures, have been identified in epilayers with a density of 1-10 cm-2. Almost all the major deep levels present in as-grown epilayers have been eliminated (< 1x1011 cm-3) by two-step annealing, thermal oxidation at 1150-1300oC followed by Ar annealing at 1550oC. The proposed two-step annealing is also effective in reducing various deep levels generated by ion implantation and dry etching. The interface properties and MOSFET characteristics with several gate oxides are presented. By utilizing the deposited SiO2 annealed in N2O at 1300oC, a lowest interface state density and a reasonably high channel mobility for both n- and p-channel MOSFETs with an improved oxide reliability have been attained.

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Periodical:

Materials Science Forum (Volumes 645-648)

Edited by:

Anton J. Bauer, Peter Friedrichs, Michael Krieger, Gerhard Pensl, Roland Rupp and Thomas Seyller

Pages:

645-650

DOI:

10.4028/www.scientific.net/MSF.645-648.645

Citation:

T. Kimoto et al., "Defect Control in Growth and Processing of 4H-SiC for Power Device Applications", Materials Science Forum, Vols. 645-648, pp. 645-650, 2010

Online since:

April 2010

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$38.00

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