Materials Science Forum Vols. 679-680

Abstract: APEI, Inc. designed, fabricated and tested a high gain AC coupled differential amplifier based on a custom-built silicon carbide (SiC) vertical junction field effect transistor (VJFET). This SiC differential amplifier is capable of extreme temperature operation up to 450 °C, at which a high differential voltage gain of more than 47 dB is maintained. This high gain AC coupled differential amplifier can be integrated with high temperature sensors that deliver weak AC output signals to improve signal quality and noise immunity.

Abstract: This paper describes a simple fault protection system for Current Source Inverter built with normally-on SiC JFETs. Because all transistors are in on-state after loss of the gate drive(s) supply, list of possible fault modes is extended in reference to standard inverters. That is also why an additional normally off switch is introduced in the DC link. Operation principles of the protection system which follows the drain-source voltages of JFETs and the current of the DC link are presented. The 2kVA/100kHz model of the inverter equipped with the proposed system is validated via various laboratory tests including short-circuits and the auxiliary supply turn off.

Abstract: This work demonstrates that a stable voltage reference with temperature, in the 25°C-300°C range is possible using SiC bipolar diodes. In a previous work, we have been demonstrated both theoretical and experimentally, the feasibility of SiC bandgap voltage reference using SiC Schottky diodes [1]. The present work completes the investigation on SiC bandgap reference by the using of SiC bipolar diodes. Simulated and experimental results for two different SiC devices: Schottky and bipolar diodes showed that the principles that govern the bandgap voltage references for Si are also valid for the SiC. A comparison between the output voltage levels of the two types of bandgap reference is also presented.

Abstract: In this work, a 4H-SiC lateral PNP transistor fabricated in a high voltage NPN technology has been simulated and characterized. The possibility of fabricating a lateral PNP with a current gain larger than 1 has been investigated. Device and circuit level solutions have been performed.

Abstract: We present first results on power cycling of 6.5 kV SiC PiN-diodes mounted into a molded package. The geometry of this lateral package was designed to fulfill the specifications of the electrical isolation and the creepage distances in the high voltage region of 6.5 kV. To evaluate the suitability of this package we used high voltage SiC PiN-diodes. The diodes were soldered onto a copper lead frame, wire bonded and covered by molding compound. The packaged diodes were characterized by electrical measurements before and during a power cycling test with a temperature swing of 90 K. These results showed long term stable behavior of the I-V characteristics of the diodes as well as the suitability of the package for high temperature and high voltage application of SiC devices.

Abstract: Local current transport across graphene/4H-SiC was studied with nanometric scale lateral resolution by Scanning Current Spectroscopy on both graphene grown epitaxially on 4H-SiC(0001) (EG-SiC) and graphene exfoliated from highly oriented pyrolitic graphite and deposited on 4H-SiC(0001) (DG-SiC). The study revealed that the Schottky barrier height (SBH) of EG/4H-SiC(0001) is lowered by ~0.49eV. This is explained in terms of Fermi-level pinning above the Dirac point in EG due to the presence of positively charged states at the interface between Si face of 4H-SiC and carbon-rich buffer layer. Furthermore, Scanning Capacitance Spectroscopy based method allowed evaluating local electron mean free path (lgr) in graphene. lgr in EG-SiC was observed to be, on average, ~0.4 times that in DG-SiC and exhibited large point-to-point variations due to presence of laterally homogeneous positively charged buffer layer at the interface. However, lgr in graphene on SiC was observed to be larger than on standard SiO2 samples (DG-SiO2), which is explained by better dielectric screening of charged impurities and lower surface polar phonon scattering at the graphene/substrate interface.

Abstract: As a new graphene functionality applicable to post-implantation high temperature annealing of SiC, a method of in situ formation and removal of large area epitaxial few-layer graphene on 4H-SiC(0001) Si-face is proposed. It is demonstrated that the homogeneous graphene layer formed by Si sublimation can be preserved without the decomposition of the underlying SiC substrate even in the excess of 2000 oC in ultrahigh vacuum. It is due to the existence of the stable (6√3×6√3) buffer layer at the interface. To ensure this cap function, the homogeneity of the interface must be guaranteed. In order to do that, precise control of the initial SiC surface flatness is required. Si-vapor etching is a simple and versatile SiC surface pre/post- treatment method, where thermally decomposed SiC surface is compensated by a Si-vapor flux from Si solid source in the same semi-closed TaC container. While this Si-vapor etching allows precise control of SiC etch depth and surface step-terrace structures, it also provides a “decap” function to remove of the graphene layer. The surface properties after the each process were characterized by AFM and Raman spectroscopy.

Abstract: Epitaxial graphene was grown on Si-face 4H-SiC. A SiC pretreatment with a carbon cap¬ping technique was used as well as slow heating rates and a temperature of 1800 °C under atmos¬pheric argon pressure. The surface morphology was investigated by atomic force microscopy and Raman spectroscopy was performed for samples with different graphitization times.

Abstract: The growth of epitaxial graphene on C-face 6H-SiC substrates is investigated using pro-cess conditions that can form small, local areas of graphene. The thickness of SiC lost to Si sublimation is not completely countered by the thickness of the resulting graphene and so graphene-covered basins (GCBs) are formed. The GCBs are most likely nucleated at threading dislocations from the substrate. The GCB morphology exhibits ridges, similar to those found on continuous films. The GCBs expand through erosion of the surrounding SiC substrate walls, eventually coalescing into continuous films. The ratio of the Raman D and G peaks was used to estimate the crystallite length scale and it was found to be about 200 nm for small GCBs and > 1 m for continuous films.