Materials Science Forum Vols. 679-680

Abstract: An optically controlled power switch based on 4H-SiC Trenched and Implanted Vertical JFETs (TIVJFET) was developed that comprises three parts: an LED light-source driver, light-triggered integrated gate buffer driver, and vertical high power normally-off switch. The light-triggered integrated gate buffer driver includes a photodiode and four stages of low voltage 4H-SiC TIVJFETs, which are hybrid integrated. Optically gated power switching was experimentally demonstrated with a maximum switching frequency of about 50 kHz, the system performance limiting factors were clearly identified and experimentally confirmed, and ways to substantially increase the switching frequency were shown. From calculations, based on realistically possible system parameters values, it could be seen that a maximum switching frequency around 1 MHz is theoretically possible with a proper choice of light source, detector, and buffer transistor parameters.

Abstract: SiC MESFETs were scaled both laterally and vertically to optimize high frequency and high power performance. Two types of epi-stacks of SiC MESFETs were fabricated and measured. The first type has a doping of 3×1017 cm-3 in the channel and the second type has higher doping (5×1017 cm-3) in the channel. The higher doping allows the channel to be thinner for the same current density and therefore a reduction of the aspect ratio is possible. This could impede short channel effects. For the material with higher channel doping the maximum transconductance is 58 mS/mm. The maximum current gain frequency, fT, and maximum frequency of oscillation, fmax, is 9.8 GHz and 23.9 GHz, and 12.4 GHz and 28.2 GHz for the MESFET with lower doped channel and higher doping, respectively.

Abstract: DMOSFETs fabricated in 4H-SiC with capabilities for blocking in excess of 1700V and conducting 20A continuous current in the on-state are presented. These SiC DMOSFETs remain functional to temperatures in excess of 225°C, with leakage current at 1700V at 225°C of less than 5 A with VGS = 0V. The DMOSFETs show excellent switching characteristics, with total switching energy of 1.8 to 1.95 mJ over the entire temperature range of testing (25°C to 200°C), when switched from the blocking state at 1200V to conducting at 20A in a clamped inductive load switching circuit. The electrical characteristics are compared to commercially available Si IGBTs rated to 1700V with similar current ratings as the SiC DMOSFET described herein.

Abstract: Doubly-implanted SiC vertical MOSFETs were fabricated displaying a blocking voltage of 4.2kV and a specific on-resistance of 23 mΩ-cm2, on a 4.5mm x 2.25mm device. Design variations on smaller (1.1mm x 1.1mm) devices showed on-resistance as low as 17 mΩ-cm2 with a blocking voltage of 3.3kV. Analysis is presented of the on-resistance and temperature dependence (up to 175°C), as well as switching performance. Switching tests taken at 1000V and 6A showed turn-on and turn-off transients of approximately 20-40ns.

Abstract: Equivalent sized (4.5 mm2 die area), 1200 V, 4H-SiC, vertical trench Junction Field Effect Transistors (JFETs) were characterized in terms of DC and switching performance. The 100 mΩ Enhancement-Mode (EM) JFET was found to have natural advantages in safe operation being normally-off, whereas the Depletion-Mode (DM) JFET was found to have advantages with ~ twice as high saturation current, less on-resistance (85 mΩ) and no gate current required in the on-state. The JFETs were found to both have radically less (five to ten times) switching energies than corresponding 1200 V Si transistors, with the DM JFET and EM JFET having EON and EOFF of only 115 µJ and 173 µJ, respectively when tested at half-rated voltage (600 V) and 12 A.

Abstract: 3C-SiC MOSFET with 200 cm2/Vs channel mobility was fabricated. High performance device processes were adopted, including room temperature implantation with resist mask, polysilicon-metal gates, aluminium interconnects with titanium and titanium nitride and a specially developed activation anneal at 1600°C in Ar to get a smooth 3C-SiC surface and hence the expected high channel mobility. CVD deposited oxide with post oxidation annealing was investigated to reduce unwanted oxide charges and hence to get a better gate oxide integrity compared to thermally grown oxides. 3C-SiC MOSFETs with 600 V blocking voltage and 10 A drain current were fabricated using the improved processes described above. The MOSFETs assembled with TO-220 PKG indicated specific on-resistances of 5 to 7 mΩcm2.

Abstract: The 1.2 kV SiC JFET and BJT devices have been investigated and compared with respect to total losses including the gate driver losses in a DC-DC converter configuration. The buried grid, Normally-on JFET devices with threshold voltage of -50 V and -10V are compared to BJT devices with ideal semiconductor and passivating insulator interface and an interface with surface recombination velocity of 4.5•104 cm/s yielding agreement to the reported experimental current gain values. The conduction losses of both types of devices are independent of the switching frequency while the switching losses are proportional to the switching frequency. The driver losses are proportional to the switching frequency in the JFET case but to a large extent independent of the switching frequency in the BJT case. The passivation of the emitter junction modeled here by surface recombination velocity has a significant impact on conduction losses and gate driver losses in the investigated BJT devices.

Abstract: We investigated the 4H-SiC C-face MOS interface properties around valence-band, and fabricated 4H-SiC C-face p-channel MOSFETs for the first time. For C-face p-channel MOSFETs, relatively low-temperature wet-gate-oxidation was preferable. Post-deposition-annealing for contact metal was found to degrade the C-face MOS interface around valence-band. Low-temperature (800°C) PDA in hydrogen including ambient was effective to some extent in order to suppress the degradation owing annealing. We obtained C-face p-channel MOSFET with normal FET operation by utilizing 900°C wet-gate-oxidation and 800°C PDA in He-H2 forming gas ambient.

Abstract: We introduce the vacuum field-effect transistor (VacFET), the first SiC FET to use a vacuum-sealed cavity in place of the traditional, solid gate dielectric. This device architecture eliminates the need to thermally oxidize the SiC surface, a practice which has been widely reported to inhibit the performance and reliability of SiC MOSFETs. Using a combination of batch-compatible electronics and micromachining processing techniques, a polycrystalline SiC bridge is suspended above a 4H-SiC substrate, and the underlying cavity is sealed under vacuum. The fundamental studies made possible by such a device could shed much-needed light on the basic electronic properties of an inverted SiC surface. In this introductory report, we detail the analytical design and fabrication necessary to manufacture the VacFET, and we also demonstrate proof of the concept using turn-on and output characteristics of the first functional SiC device.

Abstract: In this work, we succeeded in developing high performance normally-off SiC buried gate static induction transistors (SiC-BGSITs). To achieve the normally-off characteristics, design parameters around the channel region were optimized and process conditions were improved to realize these parameters. The off-state characteristic of the SiC-BGSIT showed an avalanche breakdown voltage of VBR=980 V at a gate voltage of VG=0 V. Furthermore, the leakage current at VD=950 V is lower than 0.5 μA. These results indicate that the BGSIT has a good normally-off characteristic. At VG=2.5 V, an on-resistance of 28.0 mΩ corresponding to the specific on-resistance of 1.89 mΩ•cm2 was obtained and the current rating was calculated as 33 A at a power density of 200 W/cm2 in the on-state characteristic.