Materials Science Forum Vols. 679-680

Abstract: This work presents the progress in developing an all SiC based power module for use in high frequency and high efficiency applications. Using parallel combinations of 1200V enhancement mode SiC VJFETs (36mm2) and Schottky diodes (23mm2), a total on-resistance of only 10mOhm (2.7m-cm2) was achieved at ID=100A in a commercially available standard module configured as a half-bridge circuit. Careful attention to module layout, gate driver design, and the addition of optimized snubbers resulted in excellent switching waveforms with low total switching losses of 1.25mJ when switching 100A at 150oC.

Abstract: A 1200 V SiC JFET has been demonstrated to achieve ultra-low switching losses ten times lower than for industrial grade 1200V Si IGBT. The low switching losses are also shown to compete with the fastest 600V class MOSFET in the market, yielding 1.1% higher PFC stage efficiency for 340 kHz switching frequency, when same device on-resistances were measured. The proposed normally-on JFET also differentiates over the IGBT by its purely Ohmic output characteristics without any voltage threshold, and by a monolithically integrated body diode with practically zero reverse recovery. In this paper we outline as well how the other pre-requisites for a 1200 V SiC switch in applications such as photovoltaic systems and UPS can be fulfilled by the proposed JFET solution: long-term reliability, product cost optimization by low specific on-resistance combined with reasonable process window expectations. Finally, a normally-off like safe operation behavior is ensured by a dedicated driving scheme utilizing a low-voltage Si MOSFET as protection device at system start-up and for system failure conditions.

Abstract: Numerous high-voltage applications require symmetrical bi-directional power flow control and protection circuitry. While mechanical contactors and circuit breakers provide bi-directional fault protection, they have slow actuation and suffer severe degradation during repeated fault isolation. The normally-on (N-ON) SiC vertical-channel Junction-Field-Effect-Transistor (VJFET) is an efficient solution for bi-directional circuit-breaker applications due to its low conduction/switching losses, +500°C operational capability, ON-state match of the no-fault operating mode of the system, efficient gate-drive operation under unipolar biasing, and majority carrier device scalability. Efficient 600-V/10-A symmetrical bi-directional power flow was demonstrated using 0.1-cm2 1200-V rated N-ON VJFETs with a gate driver applying 0-V and -34 V gate biases during the ON and OFF states, respectively. A self-aligned trenched guard-ring structure provides reliable edge termination.

Abstract: To study the mobility limiting mechanisms in (0001) 4H-SiC and 6H-SiC MOSFETs, physics based modeling of the inversion mobility of has been done. Two very different limiting mechanisms have been found for 4H-SiC and 6H-SiC MOSFETs. The mobility in 6H-SiC MOSFETs is limited by phonon scattering while the 4H-SiC MOSFET mobility is limited by Coulombic at low electric fields and surface roughness scattering at high electric fields.

Abstract: We have observed a significant increase in the instability of SiC power MOSFET ID-VGS characteristics following bias stressing at elevated temperature, similar to the effect we previously observed following an ON-state current stress. Devices stressed by elevated temperature alone exhibited very little instability compared with devices stressed with both temperature and applied bias. These results, along with other results in the literature, suggest that this increase in threshold voltage instability at elevated temperature is due to the activation of additional near-interfacial oxide traps related to an O-vacancy defect known as an E′ center. It is important to develop improved processing methods to decrease the number of precursor oxide defect sites, since an increased negative shift can give rise to increased leakage current in the OFF-state and potential device failure if proper precautions are not met to provide an adequate margin for the threshold voltage.

Abstract: Instability of metal-oxide-semiconductor field-effect transistor (MOSFET) characteristics was evaluated by DC and pulse current-voltage (I-V) measurements. MOSFETs with nirided gate oxides were fabricated on C-face 4H-SiC. Their interfaces have near interface traps (NITs) with long time constants, depending on the cooling down process after nitridation. Such devices exhibited a large hysteresis in DC I-V and a large transient current in pulse I-V measurements. These phenomena can be explained by the charge state of NITs due to capture/emission of electrons in the channel.

Abstract: 1.2 mm × 1.2 mm and 2.7 mm × 2.7 mm silicon carbide double-implanted metal-oxide-semiconductor field-effect transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. 1.2 mm × 1.2 mm DIMOSFETs were characterized from room temperature to 150°C. At room temperature, the specific on-resistance of this MOSFET was 5.7 mΩcm2 at a gate bias of 20 V and a drain voltage of 1.0 V. The blocking voltage of this MOSFET was 1450 V based on the avalanche current. At 150 °C, the specific on-resistance increased from 5.7 mΩcm2 to 9.1 mΩcm2 and the threshold voltage decreased from 4.9 V to 4.1 V. The blocking voltage increased from 1450V to 1500V. 2.7 mm × 2.7 mm DIMOSFETs were also characterized at room temperature. They showed a specific on-resistance of 8.0 mΩcm2 at a gate bias of 20 V and a drain voltage of 1 V. The blocking voltage of this device was 1550 V, which was determined by the avalanche current. The time-zero dielectric breakdown (TZDB) and time-dependent dielectric breakdown (TDDB) characteristics of 180 μm × 180 μm MOS capacitor were estimated. At room temperature (RT), TZDB was 9.3 MV/cm and the charge to breakdown value of 63% cumulative failure (Qbd) was 72 C/cm2. The temperature dependence of Qbd measurements showed that it deceased from 72 C/cm2 at RT to 14 C/cm2 at 250 °C. Switching characteristics of 1.2 mm × 1.2 mm DIMOSFETs were obtained by the double-pulse measurements. The turn-on time and the turn-off time were 36 nsec and 53 nsec, respectively.

Abstract: Back-gated field effect transistors (FETs) based on catalyst-free grown 3C-SiC nanowire (NW) were fabricated. Devices with rectifying Source (S) and Drain (D) contacts have been observed. In contrast with the ohmic-like devices reported in the literature, the Schottky contact barrier (SB) at S/ D regions acts beneficially for the FET performance by suppressing the off-current. At high positive gate voltages (>10 V), the Schottky barriers tend to be more transparent leading to ION/IOFF ratio equal to ~ 103 in contrast to the weak gating effect of the ohmic-contacted 3C-SiC NWFETs.

Abstract: Normally-ON 9.1 kV (at 0.1 mA/cm2), 1.52 x 10-3 cm2 active-area vertical-channel SiC JFETs (VJFETs), were fabricated at a 52% yield with no epitaxial regrowth and a three-step junction-termination-extension edge termination, which is connected to the gate bus through an ion-implanted sloped sidewall. The VJFETs exhibit low gate-to-source leakage currents of less than 1 nA up to VGS = -60 V, and sharp onsets of breakdown occurring at VGS ~ -80 V. The gate-to-source and gate-to-drain diodes turn on at 2.75 V, with the latter diode exhibiting higher resistance due to the thick epitaxial drift layer. To realize unipolar operation with low on-state resistance, the VJFET is designed very normally-ON which minimizes the channel resistance contribution. Consequently, threshold voltages are in the -3 V to -4.5 V range and transconductance is relatively low at < 0.36 mS. At a gate bias of 0 V, the VJFETs output a drain current of 73 mA with a forward drain voltage drop of 5 V (240 W/cm2), a specific on-state resistance of 104 mΩ-cm2, and a current gain of ID/IG = 6.4 x 109. Thus, these VJFETs are capable of efficient power switching, i.e., high current-gain voltage-controlled operation at a low unipolar resistance.

Abstract: A numerical simulation study focused on an oxide-free 4H-SiC power device that is based on a normally-off Bipolar Mode Field Effect Transistor (BMFET) structure, and therefore on the principle of conductivity modulation from minority carrier injection, is presented. Starting from a n-/n+ 4H-SiC epi-wafer, with an epitaxial layer thickness of a few microns, and considering the presently available 4H-SiC ion implantation technology, a completely planar SiC-based BMFET has been designed. Such a device has interesting features in terms of static forward and blocking I V characteristics for high power applications. The 4H-SiC fundamental physical models, such as the doping incomplete ionization and the carrier recombination processes, were taken into account during the simulations.