Materials Science Forum Vols. 679-680

Abstract: Anodic oxidation was performed to 4H-SiC in order to suppress the negative impacts on the Schottky diode characteristics. The electrochemical deposition of ZnO before and after the oxidation revealed a reduction in the number of areas with low Schottky barrier height. Before and after the oxidation, current-voltage characteristics of Ni Schottky contacts was compared, and it was found out that the characteristics were improved after the oxidation. These results suggest that the anodic oxidation is a promising technique to suppress the negative influence of the crystal defects.

Abstract: There is still little consensus regarding why low contact resistivity is achieved when Ni on n-type 4H- and 6H-SiC is annealed at temperatures of more than above 950°C. The objective of this paper is to provide an answer concerning to this question. It is has been reported that even Ni-based contacts formed in the n++ region exhibited a steep reduction of contact resistivity in an annealing temperature range > 900°C. This effect reduction cannot be explained by the carbon vacancy induced donor model (Vc model) proposed by Han and his coworkers [Appl. Phys. Lett., Vol. 79, p. 1816 (2001)]. And, it is clarified that It was observed that the surface of substrates annealed at 1000°C was not covered with not Ni2Si but with a thin layer of NiSi. Finally, a plausible model is proposed that as the result of annealing at higher temperatures, results in the formation of the a NiSi/SiC system is builtat the substrate interface, resulting in significant reduction in low causing contact resistivity to be reduced significantly.

Abstract: In this paper we demonstrate the recovery of Ohmic contacts formed on C-face 4H-SiC following high temperature post-processing. After a typical high-κ dielectric anneal in O2 for 3 minutes at 650 °C, replacing the metallization stack is revealed to significantly reduce the damage produced in the I-V characteristics. Using C-AFM we have also studied the mechanisms responsible for Ohmic contact formation, presenting a possible relationship between changes in the SiC crystal orientation and the establishment of Ohmic behaviour.

Abstract: With the aim of investigating the specific process parameters of bipolar semiconductor devices, simple mesa-terminated silicon carbide PiN diodes were designed and fabricated. The expected effect of the mesa height on the reverse behaviour could be investigated as well as the condition of the material surface. It was shown that these simple devices are well suited as test devices.

Abstract: The roughness of etched SiC surfaces must be minimized to obtain surfaces with a smooth aspect, avoiding micromasking artifacts originating from re-deposited particles during the etching process. Four varieties of masks, Al, Ni, Si and C, were deposited on the SiC surface by photolithographic process. The C structures were formed by annealing conversion of patterned thick photoresist. On these surfaces, dry etching was performed with an SF6/O2 plasma produced in a Reactive-Ion-Etching (RIE) reactor. Although a better aspect of the surface is obtained with Ni in comparison with Al mask, micromasking could also occur even with Ni if the mask design was not enough spaced out. With C and Si masks, which produce fluorides species with negative boiling temperature, smooth etched surface was obtained without micromasking, even for tight masks covering up to 90% of the SiC surface.

Abstract: To reduce the on-resistance in vertical power transistors, backside thinning is required after device processing. However, it is difficult to thin a SiC wafer with a high removal rate by conventional mechanical machining because its high hardness and brittleness cause cracking and chipping during thinning. In this study, we attempted to thin a 2-inch 4H-SiC wafer by plasma chemical vaporization machining (PCVM), which is plasma etching using atmospheric-pressure plasma. By controlling the scanning speed of the table and optimizing the oxygen percentage in the CF4+O2+He mixture gas, a maximum removal rate of 0.56 μm/min was obtained over the entire wafer. Furthermore, the surface roughness was improved after thinning. Therefore, PCVM can be used as an effective method for thinning SiC wafers.

Abstract: The sloped sidewall angle in 4H-SiC mesa structure could be controlled by a thermal etching at 900oC in chlorine (Cl2) based ambience. 4H-SiC C face with 8o off substrate was used. The SiO2 layers for the etching mask were formed by a deposited SiO2 layer or a thermally oxidized layer. Thermal etching was carried out at Cl2 ambience at 900oC for 15 minutes. The surface morphologies of the mesa structures were observed with the scanning electron microscope (SEM) and atomic force microscope (AFM). The sloped angles at the mesa sidewalls using deposited SiO2 mask and thermal SiO2 mask were about 23o and 60o, respectively. These results mean that the angle of sloped sidewall can change by mask fabrication method.

Abstract: We have developed a novel abrasive-free planarization method called catalyst-referred etching (CARE). A CARE-processed 8 deg off-axis 4H-SiC (0001) surface is investigated by cross-sectional transmission electron microscopy (TEM). The surface is composed of alternating wide and narrow terraces with single-bilayer-height steps, which are similar to the structure observed on a CARE-processed on-axis 4H-SiC (0001) surface. These results indicate that the structure appears on CARE-processed surfaces regardless of the off-cut angle.

Abstract: Catalyst-referred etching (CARE) is an abrasive-free planarization method. We used 3-inch and 2-inch 4H-SiC (0001) 4° off-axis substrates to investigate the processing characteristics that are affected by the substrate diameter. The surface roughness of the 3-inch substrate was extremely smooth over the whole substrate. The surface roughness and removal rate of the 3-inch substrate were approximately the same as those of the 2-inch substrate.

Abstract: Superior flatband voltage (Vfb) stability of SiC-based metal-insulator-semiconductor (MIS) devices with aluminum oxynitride (AlON) gate dielectrics was demonstrated. MIS capacitors with gate insulators consisting of a thick pure aluminum oxide (Al2O3) and a thin underlying SiO2 layer fabricated on n-type 4H-SiC substrates showed a positive Vfb shift due to substrate electron injection depending on the applied gate bias and the thickness of the SiO2 interlayer. This large Vfb shift was greatly suppressed for devices with AlON/SiO2 stacked gate dielectrics, suggesting that electron trapping sites in Al2O3 film were mostly compensated for by nitrogen incorporation. This finding is helpful in realizing highly reliable SiC-based MIS field-effect-transistors (MISFETs) in terms of threshold voltage stability.