Materials Science Forum Vols. 679-680

Abstract: In this work under-mask penetration of Al+ ions implanted in 4H-SiC is investigated by computer simulation based on the Monte-Carlo binary collision approximation (MC–BCA). Results indicate that a small fraction of ions, implanted normal to a (0001) 4H-SiC wafer (8° off-axis towards the {11-20}), is scattered and become channeled in the <1120> directions perpendicular to the <0001> axis. Due to this phenomenon, doped regions with concentration ≤ 10− 4 of the peak value, may extend laterally for a few µm below the edge of a SiO2 mask.

Abstract: Metal-oxide-semiconductor (MOS) capacitors and MOS field-effect transistors (MOSFETs) were fabricated on C-face 4H-SiC with post-oxidation annealing in phosphorus- containing atmosphere. POCl3/N2 annealing at 1000 °C, which is an effective condition for Si-face, did not bring any improvement in the interface state density (Dit) for C-face due to additional oxide growth. We have developed a new process sequence suitable for C-face MOS structures. As a result, the Dit near the conduction band edge was drastically decreased by the developed process to less than 3x1011 cm−2eV−1. The field-effect mobility of C-face 4H-SiC MOSFETs was effectively increased to 37 cm2/Vs. We found that the incorporation of phosphorus atoms into the SiO2/SiC interface can improve MOSFET performance not only for the Si-face but also for the C-face.

Abstract: To understand the structure of SiC–oxide interface more in detail, we propose a profiling theory of Si and C emission into SiC layer during oxidation. Simulations of the depth profiles of Si and C interstitials results in the structures analogous with those observed from a spectroscopic ellipsometry. To determine the diffusivities of Si and C interstitials, we performed capacitance–voltage measurements for examining the re-distribution profiles of nitrogen after oxidation and compared between observed and calculated profile. The calculated nitrogen profiles showed good fits to the observed ones in the case of self-diffusivity of C interstitials magnified by several 10 times for literature value. Finally, we discuss the validity of the proposed theory.

Abstract: In this work we report on the growth and preparation of 3C-SiC(111) material for metal-oxide-semiconductor (MOS) application. In order to achieve reasonable material quality to prepare MOS capacitors several and crucial steps are needed: 1) heteroepitaxial growth of high quality 3C-SiC(111) layer by vapour-liquid-solid mechanism on 6H-SiC(0001) substrate, 2) surface polishing, 3) homoepitaxial re-growth by chemical vapour deposition and 4) use of an advanced oxidation process combining plasma enhanced chemical vapour deposition (PECVD) SiO2 and short post-oxidation steps in wet oxygen. Combining all these processes the interface traps density (Dit)can be drastically decreased down to 1.2  1010 eV-1cm-2 at 0.63 eV below the conduction band. To our knowledge, these values are the best ever reported for SiC material in general and 3C-SiC in particular.

Abstract: Influence of high-vacuum annealing at temperatures in the range 1300-1400°C and residual pressure of ~10-6 Torr on the surface of 6H-SiC (0001) wafers has been studied. Auger spectroscopy and RHEED data show that the annealing conditions do not lead to any surface reconstruction of the wafers. Atomic force microscopy reveals atomically flat surface terraces separated by steps of unit-cell height (h = 1.5 nm).

Abstract: Aluminum-based high-k dielectric materials have been studied for their potential use as passivation for SiC devices. Metal-insulator-semiconductor structures were prepared and their dielectric properties were analyzed using capacitance-voltage and current-voltage measurements. Atomic layer deposition was used for the deposition of dielectric layers consisting of AlN with or without a buffer layer of SiO2, and also a stack of alternating AlN and Al2O3 layers. It has been observed that AlN has a polycrystalline structure which provides leakage paths for the current through the grain boundaries. However, adding alternate amorphous layers of Al2O3 prevent this leakage and give better overall dielectric properties. It is also concluded that the breakdown of the dielectric starts from the degradation of the thin interfacial SiO2 layer.

Abstract: Post-oxidation annealing (POA) in Ar at high temperature has been performed during fabrication of 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). The gate oxides were formed by thermal oxidation followed by N2O annealing, then annealed in Ar for 30 min or 5 h at 1300 °C. The results of Secondary Ion Mass Spectrometry (SIMS) measurements indicated that the C atoms accumulated at the SiO2/SiC interface by thermal oxidation diffused during the 5h-Ar annealing. The characteristics of n-channel MOSFETs were improved and the peak value of field effect mobility was increased to 33 cm2/Vs from 19 cm2/Vs by extending the Ar annealing time.

Abstract: We investigated the performance of different metallization/passivation systems for high temperature applications. The metallizations comprised a 150 nm sputtered Pt or a 150 nm e-beam evaporated PtRh layer on Ti/TiN underlayers, respectively. The passivation coatings consisted of amorphous PECVD SiOx, of amorphous stress-reduced PECVD SiNy, and of a SiOx/ SiNy stack. For samples with SiOx and SiOx/ SiNy passivation layers the electrical properties changed after a short high temperature anneal at 600 °C but then remained stable during further annealing. This was attributed to the formation of PtTi alloys, which stabilized the metallization stack. In samples with SiNy passivation a significant Pt out-diffusion into the passivation layer was observed. This led to a degradation of the electrical and mechanical properties. The best performance was achieved with Pt-based metallizations and SiOx or SiOx/SiNy passivations.

Abstract: In this work we studied different Schottky contacts to 4H-SiC with the aim to obtain Schottky Barrier diodes (SBDs) and Junction Barrier Schottky diodes (JBS) able to operate at high temperatures, frequencies and power densities with low power losses. Schottky contacts were fabricated using Mo and Mo/Al layers annealed up to 600 °C using a Rapid Thermal Process (RTP). A comparison with previous results obtained with Ni, Ti and Ti/Al layers annealed up to 400 °C is also proposed. The Schottky contacts were characterized by means of standard Current-Voltage (I-V) and Capacitance-Voltage (C-V) techniques. X-ray Photoelectron Spectroscopy (XPS) analyses were performed in depth profile mode in order to study the structural evolution of the interface Mo/SiC and Al/Mo during annealing treatments. Mo/Al contacts show a lower barrier height and better overall performances in forward polarization when compared to the Ti- and Ni-based contacts, and they are very promising for Schottky contact fabrication on SBD and JBS.

Abstract: In this paper, we propose a graded etched junction termination extension for SiC thyristors. It has the functionality of a multiple implanted JTE, but is realized by purely etched means. This termination is demonstrated up to 4 kV on a sample with a drift layer thickness of 35 µm. On another sample with a thinner drift layer, similar thyristors have been realized with a low resistive contact, resulting in an on-state voltage drop of 3.2 V at 40 A/cm².