Materials Science Forum Vols. 679-680

Abstract: Photo emission phenomenon and reliability of thermal oxides grown on n-type 4H-SiC (0001) wafer have been investigated using photo emission microscope. Thermal oxides were grown by dry oxidation, and treated in nitrous oxide atmosphere as followed by hydrogen post oxidation annealing. An initial photo emission phenomenon with weak intensity exists just after stress current is applied to the thermal oxide. It is confirmed that most initial emission occurred at the same position as dielectric breakdown of the thermal oxide. Also, the initial emission phenomenon was observed in the MOS capacitors broken by extrinsic defects such as threading screw dislocations and surface defects. In addition, the photo emission due to Fowler-Nordheim tunnel current through the thermal oxide has peak intensity at 2.48 eV.

Abstract: Metal-oxide-semiconductor (MOS) capacitors were formed on 4H-silicon carbide (SiC) using thermally grown silicon dioxide (SiO2) as gate dielectrics, both with and without nitrogen incorporation within the oxide. The field dependence of the charge trapping properties of these structures was analyzed and linked to the observed Fowler-Nordheim current degradation. Furthermore, first considerations were presented that indicate an electron impact emission induced generation of positive oxide trapped charge.

Abstract: The energy band structure of SiO2/4H-SiC fabricated on (0001) Si- and (000-1) C-face substrates was investigated by means of synchrotron radiation x-ray photoelectron spectroscopy (SR-XPS). The band structure was found to be dependent on substrate orientation and oxide thickness due to both intrinsic and extrinsic effects that cause charge transfer at the SiO2/SiC interface. Our SR-XPS analysis revealed that the intrinsic conduction band offset of the SiO2/SiC for the C-face substrate is smaller than that for the Si-face. This means that, whereas C-face substrates exhibit high carrier mobility, a problem that is crucial to gate oxide reliability remains for SiC-based metal-oxide-semiconductor (MOS) devices owing to increased leakage current.

Abstract: An inductively heated furnace and an ultra-fast microwave heating system have been used for performing post implantation annealing processes of P+ implanted semi-insulating <0001> 4H SiC at 1800-1950°C for 5 min and 2000-2050°C for 30 s, respectively. Very high P+ implantation fluences in the range 71019 81020 cm-3 have been studied. The annealing processes in the inductive furnace and the one at the lower temperature in the microwave furnace show a saturation in the efficiency of the electrical activation of the implanted P+ that is bypassed by the microwave annealing process at the higher temperature. The measured electron mobility values versus electron density are elevated in all the studied samples and for every post implantation annealing process. This has been ascribed to an elevated implanted crystal recovery due to the very high annealing temperatures > 1800°C.

Abstract: The simulation of the incomplete ionization of substitutional dopants in Silicon Carbide (SiC) is often performed using Boltzmann statistics and ionization energy values that do not depend on free carrier concentrations. But in the case of heavy doping Fermi-Dirac statistics is needed, while the case of an inhomogeneous dopants distribution or that of an excess carrier injection requires local free carrier concentration-dependent impurity ionization energies. Here a model for describing partial ionization from diluted to high homogeneous doping densities in SiC and in thermal equilibrium is presented and compared with results on Phosphorus doped 4H-SiC.

Abstract: The variation in device process parameters is a core issue in the realisation of complex SiC logic for extreme environments. Factorial design was used to study the effect of variation in four key process parameters on the threshold voltage of an n-channel lateral JFET. Each parameter is simultaneously varied by +/-10% from the default value and the individual and combined effects were calculated at 300, 600 and 1000K. Consequently, we show how these variations in device parameters degrade the threshold voltage, VI, and, hence, the noise margin of logic inverter.

Abstract: A two-dimensional model of aluminum-ion implantation into 4H-SiC at moderate doses (1011 to 1013 cm-2) has been developed. The model is based on a Monte-Carlo simulation using a binary-collision approximation. This simulation reveals that iso-concentration contours are independent of the orientation of the masking edge. Lateral range straggling is extracted by expressing the lateral-concentration profiles as a one-dimensional dual-Pearson-distribution function multiplied by a Gauss-distribution function. Compared to vertical straggling, the lateral straggling is found to be more weakly dependent on projected range.

Abstract: In the present paper, 4H-SiC JBS diodes with "boron" p–n junctions have been investigated by means of deep-level transient spectroscopy (DLTS). The sign of the DLTS signal for all the 4H-SiC diodes under study, was positive. The "anomaly" of the DLTS spectra measured is apparently connected with the properties of "boron" p–n junctions. In particular, is presented the role of deep D-centers in recompensation of donors in the JBS diodes.

Abstract: This paper reports on the impact of the surface morphology on the properties of Ti/Al Ohmic contacts fabricated on Al-implanted 4H-SiC. In particular, the surface roughness of the Al-implanted regions after annealing at 1700 °C was strongly reduced by the using a protective carbon capping layer during annealing (the surface roughness decreased from 9.0 nm to 1.3 nm). In this way, also the morphology and the specific contact resistance of Ti/Al Ohmic contacts formed on the implanted regions could be improved. The electrical and morphological data were correlated with the structural properties of the reacted metal layer and of the metal/SiC interfacial region.

Abstract: The impact of implantation temperature and dose as well as the annealing process with and without a graphite capping layer on surface roughness, carrier mobility and specific contact resistance are investigated and compared. The use of the capping layer is proven to be particularly advantageous: (1) a deterioration of surface roughness can be avoided even for high dose implantations and (2) the specific contact resistance is reduced. Furthermore, it is shown that a capping layer prevents surface contamination during annealing.