Materials Science Forum Vols. 679-680

Abstract: Rapid Thermal Processing (RTP) has been evaluated as an alternative to the conventional furnace process for the gate oxide formation of SiC lateral MOSFETs. We show that this innovative oxidation method has not only the advantage to significantly reduce the thermal budget compared to classical oxidation, but also produces a significant improvement of MOSFET performance when using N2O as oxidizing gas. Studying different surface preparation before gate oxidation, we demonstrate that in-situ surface preparation by H2 annealing increases considerably the channel mobility and also the electrical stability with respect to constant bias stress at low-field.

Abstract: In this study a pyrolyzed photoresist film that has been used for protecting the implanted surface of a 4H-SiC wafer during post implantation annealing at 1800-1950 °C has preserved on the wafer surface and used for the fabrication of ohmic contact pads on P+ implanted areas. The carbon film has been patterned by using a RIE O2-based plasma. A specific contact resistance of 9  10 5 cm2 has been obtained on P+ 1  1020 cm 3 implanted 4H-SiC. Micro-Raman characterizations show that the carbon cap is formed of a nano-crystalline graphitic phase.

Abstract: Cubic silicon carbide nanowires (-SiC or 3C-SiC NW) have been grown by Vapour Phase Epitaxy on (001) silicon substrates patterned by conventional photolithography and on Micro Electro Mechanical Systems (MEMS, e.g. cantilevers, springs, bridges) fabricated on (001) Silicon On Insulator (SOI) wafers. The NW morphology was investigated by scanning electron microscopy, showing that the nanowires grew selectively where a nickel thin layer was previously deposited, thanks to its catalytic action. High resolution transmission electron microscopy studies showed that the NWs are predominantly 3C polytype with <111> growth axis and stacking defects on (111) planes.

Abstract: Silicon microwires (MWs) previously synthesized using the VLS method with gold catalyst are being carburized at 1100°C under methane aiming to their conversion to SiC. SEM, TEM as well as XPS and Raman spectroscopy were used for structural and morphological characterization. After carburization achievement, SiC is found to be polycrystalline with a high density of stacking faults associated to an increase of surface roughness. Directions for the carburization process optimization are given.

Abstract: The electronic structure and absorption spectrum of hydrogenated silicon carbide nanocrystals (SiC NC) have been determined by first principles calculations. We show that the reconstructed surface can significantly change not just the onset of absorption but the shape of the spectrum at higher energies. We compare our results with two recent experiments on ultrasmall SiC NCs.

Abstract: We have investigated the absorption of 0.9, 1.4 nm silicon carbide nanoparticles (SiC NPs) by time-dependent density functional calculations, focusing on the effect of different oxygen adsorbates of the surface. We have found that negatively charged Si-O−, Si-COO− defects dramatically lower the optical gap of SiC NPs. Our findings can help interpret recent controversary experiments on colloidal SiC NPs.

Abstract: Nanocrystalline diamond (NCD)/3C-SiC layered films are deposited on Si substrates by using a moderate-pressure microwave plasma apparatus. The epitaxial 3C-SiC thin layer is grown on p-type Si(001) above 1200°C in 2%CH4/98%H2 by plasma-assisted carbonization and the n-type NCD overlayer is subsequently grown at 830°C in 1%CH4/30%N2/69%Ar by plasma-enhanced chemical vapor deposition (CVD). According to cross sectional TEM observations, the initial thickness of the 3C-SiC layer (~20 nm) is reduced to 10 nm or less in the beginning of the NCD growth due most likely to etching. A rectifying current-voltage characteristic is obtained for an n-type NCD/epitaxial 3C-SiC/p-type Si(001) junction in a diode configuration.

Abstract: The paper describes first results of 6.5 kV SiC PiN diode modules which are designed as neutral point valves for medium-voltage power inverters rated for 1000 A. The power module consists of 4 AlN DCB substrates soldered on an AlSiC base plate. Each DCB is equipped with 20 SiC PiN diodes operating in parallel. The total active area of all 80 diode chips is 5.68 cm². At the rated current of 2 x 500A the forward voltage drops from 4.1 V at room temperature to 3.9 V at an averaged junction temperature of 125°C. The switching experiments show a very low reverse recovery charge of about 30 µC only. The conduction loss is comparable to the corresponding 6.5 kV silicon diode whereas the dynamic loss is marginal with respect to the forward conduction loss if the switching frequency is held below 10 kHz.

Abstract: Forward voltage drops of carbon implanted and thermal oxidized pin diode with thick drift layer are investigated to evaluate the effect on the lifetime. The forward voltage drops of the carbon implanted and thermal oxidized pin diodes with drift layer of 120 μm thick were around 4.0 V. Furthermore, blocking characteristics of 4H-SiC pin diodes with mesa-JTE, which were fabricated on C-face and Si-face substrates, are also investigated. The breakdown voltages of pin diodes with 250 μm and 100 μm epitaxial layers are 17.1 kV and 10.9 kV, respectively.

Abstract: We report on specific features of forward voltage degradation of 4H-SiC p-i-n diodes in the pulse mode. It is shown that pulse stresses with a pulse duration shorter than several milliseconds cause substantially smaller forward voltage drift in comparison with a dc stress with the same charge passed through the diodes and the same distribution of injected carriers. A self-recovery of the forward voltage is observed at room temperature.