Solid State Phenomena Vols. 145-146

Abstract: Recently, the control of particles measured in the tens of nanometers has become indispensable for manufacturing semiconductor devices. In sulfuric acid - hydrogen peroxide mixture (SPM) processes, it is increasingly important to reduce particles on the wafer. A batch type re-circulation bath has been generally used with a fluoroplastic filter built into the equipment. The pore size of the filter used has gradually become smaller. The particle levels on the wafer have decreased after the filter was changed from a 100nm rating to a 30nm rating.

Abstract: To achieve uniform copper plating on the surface of the wafer consistently in a production lot, a particle-free plating solution must be presented to the wafer under uniform pressure, uniform flow and at the proper formulation. This is accomplished by recirculating large volumes of the plating solution past the surface of the wafer. It is important that the chemistry of the solution remains uniform during the copper plating process to ensure repeatable performance. To maintain a low particle level, the fluid is filtered in a recirculated mode at a high flow rate. The filter must have low pressure drop, good particle retention and high throughput to result in low wafer defects and high system uptime. In addition, the proper filter must be selected so that it doesn’t absorb or remove desirable components like additives as it removes contamination from the solution.

Abstract: Interfacial interaction forces between particulate contaminants and semiconductor wafer surfaces play a key role in the understanding of post-CMP and post-lapping cleaning processes. In order to facilitate removal and prevent re-deposition of submicron particles on wafer surface, understanding, measurement, and manipulation of these forces is required. The theory of interaction forces in liquids that includes DLVO forces (van der Waals, electrical double layer) and non-DLVO (solvation, hydration, hydrophobic, steric and bridging forces) is well established and is studied elsewhere.1-4 Short range interaction forces between silica surfaces in alcohols have been successfully measured before using AFM.5-7

Abstract: Nanostructures with high aspect ratios, HAR, (ratio of height to lateral feature size) are of interest for many applications. One of the immediate advantages is the large surface area of these structures. In the field of DRAM manufacturing for example, the capacitance of cylindrical DRAM capacitors increases linearly with height. Wet etching and drying of these fragile high aspect ratio structures without lateral collapse (stiction) is a big challenge for the fabrication of DRAM capacitors. The problem with HAR structures is stiction during drying [1]. In order to reduce stiction by improvement of drying techniques, a good metric to quantify the occurrence of stiction is needed. However, currently used methods like SEM or brightfield defect inspection are extremely time-consuming.

Abstract: As the critical dimension of LSI continues to decrease, the surface tension of water and its effect on the formation of watermarks is becoming a significant problem. It is known that watermarks are easily generated when a silicon hydrophobic surface is dried in a wet cleaning process. Many studies about watermarks have been reported [1, 2]. Additionally if the rinse and dry steps were performed under an inert (nitrogen) ambient and the rinse water had low oxygen concentration, watermarks could be effectively avoided [3, 4].

Abstract: The continuous dimensional reduction drives the development of metrology, analysis and characterization for nano and micro electronics. An enormous worldwide R&D effort focuses on the understanding and controlling materials properties and dimensions at atomic level. Crucial for groundbreaking new developments is the availability of appropriate analytical infrastructures providing techniques with information depths well adapted to the nanoscaled objects of interest. This requires widely accessible, independent complementary metrology, analytical techniques, and characterization. For example new materials and the demand of improved detection sensitivities for contaminants provide huge challenges for the capabilities of current analysis equipment and expertise. At the same time, the availability of complementary competences is crucial for advancement of analytical methodologies through cross-comparison, round-robin, and benchmarking of results. This paper describes the formation of an independent analytical infrastructure within Europe having the expertise and competence to solve metrology problems for development of nanotechnologies. Furthermore, a strategy is shown to establish independently operating ‘Golden Laboratories’ for complementary and reliable metrology, analysis, and characterization adapted to the requirements of industrial partners.

Abstract: As the detection of inorganic contaminants is of steadily increasing importance for the improvement of yields in microelectronic applications, the aim of one of the joint research activity within the European Integrated Activity of Excellence and Networking for Nano- and Micro-Electronics Analysis (ANNA, site: www.ANNA-i3.org) is the development and assessment of new methodolo¬gies and metrologies for the detection of low concentration inorganic contaminants in silicon and in novel materials. A main objective consist in the benchmarking of various analytical techniques avail¬able in the laboratories of the participating ANNA partners, including the improvement of the res¬pective detection limits as well as the quantitation reliablity of selected analytical techniques such as total-reflection x-ray fluorescence (TXRF) analysis.

Abstract: In the semiconductor industry, the edge exclusion of processed wafers is decreasing to accommodate more integrated circuits. With this trend, there is a higher risk of detrimental contamination at the wafer edge and bevel making the monitoring for metallic contamination in these areas critical. Cross contamination from the edge and bevel can occur at many processing steps. For example, metals can spread from the wafer edge, bevel and backside to the wafer’s surface in a wet cleans process. In immersion lithography, the water drop that is scanned across the wafer could transport contamination from the edge and deposit it across the wafer surface. Contamination on wafer edge and bevel can have many origins; handling systems in every process tool, reaction products in etching, and residuals of new materials in high-k for CVD and PVD, for example. To know what metallic contamination is present, and to investigate the causes are essential for wafer edge control.

Abstract: The monitoring and optimization of wet clean and surface preparation processes is a major challenge in the microelectronics industry [1, 2]. Today, the main methods used in clean rooms are visual inspection by light scattering (principally applied to particle detection) and metallic contamination detection by Total-reflection X-Ray Fluorescence (TXRF). These methods, despite good sensitivity and recent progress [3, 4] are not sufficient, especially considering non-visual defects not measurable by light scattering, nor TXRF due to their chemical nature or to their size and location (TXRF is not applicable to light elements – with Z < 11 – and is typically a 1 cm resolution tool, with 1 to 2 cm edge exclusion). Non-vibrating Surface Potential Difference Imaging (SPDI), introduced in 2005 under the name of ChemetriQ® is an in-line, non-contact, non-destructive inspection technique based on the imaging of surface Work Function (WF) lateral non-uniformities [5]. Recent studies show very promising results for SPDI: high sensitivity to traces of metals on Si wafers with native oxide [6]; fast imaging capabilities of unpatterned or patterned wafers with sensitivity to chemical residues and charge [7, 8]. In this work, the ChemetriQ method is evaluated for in-line control of wet clean processes. The variation of SPDI data from various contaminants is compared to intra- and inter-wafer variations related to the cleaning and measurement conditions. Note that all wafer maps are presented with the notch oriented at 6:00.

Abstract: Contamination control has become a high-centered issue for the fabrication yield, performance and reliability of leading-edge ULSI devices. With the progress of sizing down dimensions in higher-density devices, complicated device structures and various novel electronic materials have been introduced, particularly in the latest devices such as CMOS and nonvolatile memory LSIs (Table I). On the other hand, high productivity is a necessity when you consider QTAT (quick turnaround time) and cost-effective flexible ULSI manufacturing lines. Therefore, effective contamination control coupled with adequate protocol has become essential in such production lines. The point of the protocol is minimization of damage caused by impurity metals diffused from these novel electronic materials [1-5].