Solid State Phenomena Vols. 145-146

Abstract: The formation of self-assembled monolayers (SAMs) by specific organic molecules with appropriate anchor groups on semiconductor surfaces may be used to probe the chemical state and quality of the surface or to achieve surface passivation. Molecules with thiol anchor groups are able to bond to hydrogen-terminated germanium surfaces (Ge-S bond). We have prepared SAMs of alkylthiols with different head groups on germanium. Since the surface preparation of germanium is neither well understood nor developed, the controlled preparation of an oxide-free completely H-terminated surface which is a prerequisite for SAM formation of alkylthiols turned out to be a major challenge. Several approaches have been studied. The characterization of the germanium surface prior to and after SAMs formation has been performed by AFM, XPS, Synchrotron-TXRF and -NEXAFS.

Abstract: Strained silicon engineering was first used at the 90-nm node. Nowadays, a series of techniques has seen wide-spread use and many derivatives are available because of their ease of integration and cost-effective features [ , ]. As a main part of stressor technique, embedded SiGe-S/D technology is reported to improve the pMOSFET drive current [ , ].

Abstract: Several device concepts have been further evaluated after the successful implementation of epitaxial Si, SiGe and/or Si:C layers. Most of the next device generations will put limitations on the thermal budget of the deposition processes without making concessions on the epitaxial layer quality. In this work we address the impact of ex-situ wet chemical cleans and in-situ pre-epi bake steps, which are required to obtain oxide free Si surfaces for epitaxial growth. The combination of defect measurements, Secondary Ion Mass Spectroscopy, photoluminescence, lifetime measurements, and electrical diode characterization gives a very complete overview of the performance of low-temperature pre-epi cleaning methods. Contamination at the epi/substrate interface cannot be avoided if the pre-epi bake temperature is too low. This interface contamination is traceable by the photoluminescence and lifetime measurements. It may affect device characteristics by enhanced leakage currents and eventually by yield issues due to SiGe layer relaxation or other defect generation. A comparison of state of the art 200 mm and 300 mm process equipment indicates that for the same thermal budgets the lowest contamination levels are obtained for the 300 mm equipments.

Abstract: The well known wet chemical treatments of the silicon surface and its native oxidation in air cause a high density of interface states, which predominantly originate from dangling bonds strained bonds or from bonds, between adsorbates and silicon surface atoms. Therefore, a number of wet-chemical treatments have been developed for ultraclean processing in order to produce chemically and electronically passivated surfaces [1]. The saturation of dangling bonds by hydrogen removes the surface states and replaces them by adsorbate-induced states, which influence the surface band-bending [2]. The first thermal hydrogen desorption peak from a hydrogen passivated Si surface in vacuum or inert gas ambient can be detected at around 380°C [3,4]. Simultaneously the combination of the hydrogen atoms of neighboring dihydrides generates a pair of dangling bonds. At around 480-500°C dangling bonds are generated on the silicon surface by desorption of the remaining hydrogen [5]. At that moment the silicon surface becomes extremely reactive.

Abstract: While batch wafer cleaning processes have been conventionally used in the semiconductor manufacturing for many years, the use of single wafer cleaning processes in the manufacturing has recently become increasingly widespread. Single wafer cleaning processes have the advantages of reducing particle and metal contamination, however, electric charge or electrostatic discharge phenomena occurring in these processes causes serious problems such as device destruction through insulation failure and circuit disconnection [1,2]. Well-known examples are the breakdown of the ultra-thin gate oxide and the dissolution of Cu wiring due to charging-up damage in de-ionized water rinsing, which occur during the single wafer wet cleaning process in semiconductor manufacturing. We investigated the problem of wafer defects caused by electrostatic discharge and characterized them using transmission electron microscope (TEM) and energy dispersive X-ray (EDX) analyses.

Abstract: With a progress of device dimension miniaturization, an ultraclean wafer surface is continuously increasing its importance crucial for high quality processing in Silicon Technologies [1]-[8]. Cleaning of silicon wafer surface has been accomplished by RCA wet cleaning in the past [9], where there exists high temperature processes consisting of H2SO4/H2O2/H2O, NH4OH/H2O2/H2O and HCl/H2O2/H2O treatments. Thus, RCA cleaning requires a large number of processing steps, resulting in the consumption of a huge volume of liquid chemicals and UPW, and simultaneously consuming a large volume of clean air exhaust to suppress chemical vapor from getting into the clean room. Moreover, RCA cleaning is used at high temperature and contain alkali solutions, which increase the roughness of the silicon wafer surface [10].

Abstract: As a design rule of memory devices is scaled down to sub-100 nm, shallow trench isolation (STI) technology is faced with gap-filling problem in case of CVD oxide and O3-TEOS oxide processes. To overcome the gap-filling problem, a perhydropolysilazane (PHPS) based spin-on dielectric (SOD) has been implemented for nanoscale devices because of self-planarization and excellent gap-filling property [1]. However, the stability of the SOD has been concerned about because it has relatively softer and more porous than conventional HDP oxide. In this paper, we report the effect of wet oxidant treatment on the stability of the SOD for STI gap-filling.

Abstract: Tungsten is a metal widely used for interconnections. As a consequence of more stringent requirements in terms of aspect ratio deriving from device shrinking, the filling of W plugs is becoming more and more critical and new deposition techniques need to be employed to properly fill contacts and trenches. For example ALD nucleation layers need to be coupled to CVD deposition. Since physical-chemical properties of W are heavily influenced by deposition techniques, the effect of wet cleanings on different kind of W needs to be fully understood in order to avoid any kind of W corrosion or recession during wet cleaning with W exposed. In this paper the effect of several chemicals commonly used in BEOL wet cleanings for polymer removal, has been investigated on W films deriving from both CVD and ALD deposition techniques.

Abstract: The Si transistor has dominated the semiconductor industry for decades. However, to fulfill the demands of Moore’s law, the Si transistor has been pushed to its physical limits. Introducing new materials with higher intrinsic carrier mobility is one way to solve this problem. Ge, GaAs and InGaAs are known for their high mobilities and are therefore suitable candidates for replacing Si as a channel material. However, introduction of new materials raises new issues. For Si processing, several steps such as cleaning, etching and stripping are based on wet treatments. The knowledge of etch rates of the semiconductor material is of great importance. In this paper, etch rates of Ge, GaAs and InGaAs in several chemical solutions are studied. A comparison of the etch rates is made between the materials.

Abstract: With the continuous down scaling features sizes, the need of speed increase and power consumption reduction start to be more and more critical. The classical integration scheme of poly silicon gate on CMOS devices does not meet the requirements of the 45 nm technology node and beyond. On this matter, new materials and different integration flows are being investigated in order to improve the device performance. High-k materials associated with metals are actively investigated as new gate materials in which different integration approaches like metal gate first or metal gate last are proposed [1].