Solid State Phenomena Vols. 145-146

Abstract: In this paper, a case of molybdenum contamination from wet cleaning is discussed, and various techniques are compared for their ability to detect molybdenum. In addition, the impact of this sort of contamination on the electrical results of a bipolar device is studied.

Abstract: This work details the investigation of potential problems in Complimentary BiCMOS technology, especially PNP transistors arrays. Optical examination of the wafer revealed defects in the P Buried Layer (PBL) areas of the die. Electrical testing correlated these PBL defects to PNP array current leakage. As the PBL module is completed very early on in the process, we devised a shortloop (SL) to reproduce these defects and identify the root cause of current leakage.

Abstract: The impact of metal-ion contamination (present on wafer surface before oxidation) on gate oxide integrity (GOI) is well known in literature, which is not the case for clean silica particles [1, 2]. However, it is known that particles present in ultra-pure water (UPW) decrease the random yield in semiconductor manufacturing [3]. The presence of silica in UPW is common knowledge. UPW has also a certain content of metal ions, which can be attached to silica. That means, when a wafer is in contact with UPW metal ion can directly and/or in form of a silica-metal conglomerate be attached to the wafer surface. That means, it is not known in which form metal-ion contamination will deteriorate GOI the most. In order to receive more clarity in this field a short-loop study was set up, where we want distinguish between the impacts of - low metal ion contamination (Calcium), - clean silica particles (330nm) contamination, - silica particles with metal-ion core (330nm) contamination, and - metal-ion contamination at similar concentration as the metal-ion core of the particles on GOI (uniform and none uniform distribution).

Abstract: As a result of shrinking dimensions and technology nodes, nanoelectronics manufacturing and handling processes demand growing requirements to the cleanliness of the air inside cleanrooms and microenvironments. Besides the limitation of particle contamination, the limitation of airborne molecular contamination (AMC) is necessary to ensure yield and quality of nanoelectronics production lines.

Abstract: With decreasing critical size of micro-electronic fabrication imposed by ITRS today, Front Opening Unified Pod (FOUP) has been designed to transport the silicon wafers in the 300 mm semiconductor fab to decrease the particles contamination, without taking the Airborne Molecular Contamination (AMC) and moisture problems into account. Various methods of AMC decontamination methods has been introduced in past, such as purging mini-environment with nitrogen, however the efficiency of its yield improvement capacity has not been proven. An ultimate AMC decontamination method with vacuum decontamination and passivation technology shows a very good efficiency on the AMC removal mechanism, with a direct impact on the yield improvement.

Abstract: Today, the use of Pods or FOUPs (Front Opening Universal Pod) in IC manufacturing leads to specific molecular contamination issues related to the enclosed environment made with porous polymers (mainly PEEK, PC and PP) that constitute these containers. Indeed, such materials are known to outgass airborne molecular contaminants (AMC), especially polymers additives [1,2]. They are also able to absorb volatile compounds present in their atmosphere coming from the connection to an equipment or from the release of wafers just processed [3,4]. As a result, a reversible outgassing of species previously trapped in plastic is possible. This is especially critical in presence of wafers sensitive to the released contaminants leading then to potential detrimental impacts. This cross-contamination scheme was clearly evidenced for volatile acids in presence of Cu layers leading to corrosion issues [4].

Abstract: The present work reports a method to prevent the condensation defects on contact hole patterns by improving the rinsing process after a dry etching. In general, residual gases on the surface after the dry etching can be easily removed by using a DI water rinse. However, the residual gas can not be completely removed in high aspect ratio contact holes, resulting in the condensation defect. In this work, in order to completely remove the residual gas inside the contact holes, several rinse processes were employed such as a megasonic rinse, a sequential rinse and a hot temperature rinse. These proposed rinse methods were effective in eliminating the residual dry etching gases in the high aspect ratio contact holes and thus were able to remove condensation defects on contact holes.

Abstract: The interaction between photo resist and highly polymerizing dry etch chemistries results in the deposition of fluoropolymers on the bevel and edge of silicon wafers. These polymers are inert to most aqueous processing chemicals, but exposure to HF lifts these polymers off the bevel. This results in migration of defects to the face of the wafers. The defects are generally found within 50mm from the edge of the wafer.

Abstract: After technical results presented the last two years and new results on volatile contamination, this paper reviews the contamination management in advanced microelectronic and proposes rules for advanced Integrated Circuits (IC) manufacturing. The competitiveness of a production line is insured only if right contamination management rules are applied. These rules must allow a fast introduction of disruptive technologies while keeping as low as possible associated costs: processing on shared equipments, determination of acceptable levels of contamination with a good understanding of their detrimental impact on devices, knowledge on contamination dissemination mechanisms. Moreover, a control of contamination using appropriate cleanings and metrologies is mandatory.

Abstract: III-V compound semiconductors have been recognized among the potential options for continuing transistor power-performance scaling owing to their ultra high charge carrier mobility. In order to realize their potential in high performance and lower-power digital logic applications, there must be strong gate control and a high Ion-Ioff ratio, achieved by integrating a stable, ultra thin high-K dielectric between the semiconductor and the gate [1, 2]. Unlike Si, which has long benefited from its very stable native oxide, III-V materials suffer from their poor native oxides that cause charge traps and Fermi level pinning at the semiconductor-oxide interface. Attempts to deposit high-K directly on III-V often produce MIS structures with fast surface state and CV instability [3].