Solid State Phenomena Vols. 145-146

Abstract: NiPt self-aligned silicide (salicide) has become a major candidate for the 45nm node due to its better thermal stability and the surface morphology of NiSi on Si substrate [1,2]. SiGe has been proposed for PMOS strain engineering [3]. The relevant SiGe oxidation behavior [4], reaction with platinum [5] and thermal stress behavior [6] are important factors in developing a process for 45nm NiPt salicide over SiGe stressor. These concerns require the review of the current process for NiPt to verify its compatibility and extendibility.

Abstract: High-k gate dielectrics (HK), such as HfO2 or HfSiON, are being considered as the gate dielectric option for the 45nm node and beyond. In order to alleviate the Fermi-level pinning issue and to enhance the CET (Capacitive Effective Thickness) by generating the depletion layer in poly-Silicon gate, metal gate electrodes with proper work functions (WF) have to be used on the high-k dielectrics.

Abstract: Integrating multiple gate oxides on a same die requires a proper definition of their respective active area (fig. 1). First the thick gate oxide is grown, and covered by some photoresist. Then a wet etch removes this oxide on the die areas where the resist has been developed. Finally, after resist stripping and surface cleaning, the thin gate oxide is grown. The interaction between the thick oxide surface, the resist and the etchant makes the wet etch challenging. This paper deals with some characterizations and solutions to improve this process.

Abstract: Recently, plasma-less gaseous etching processes have attracted attention for their interesting etching properties. Previously, we reported on the etching properties of theses processes for various kinds of oxides and revealed that they reduce the etch rate of the chemical-vapor-deposited (CVD) oxides more than the conventional wet etching process does [1]. Our results also revealed that depressions called divots in the CVD oxide of the shallow trench isolation (STI) became smaller in size by substituting a plasma-less gaseous etching process for the conventional wet etching process. In semiconductor manufacturing, many processes are used to remove oxides damaged during ion implantation or reactive ion etching on the device surface. Therefore, it is very important to understand the etching properties of plasma-less gaseous etching processes for damaged oxides as well as those for other kinds of oxides. In this report, we evaluate the etching properties of one particular plasma-less gaseous etching process for oxide films damaged during the ion implantation process under various conditions and discuss the mechanism of interesting etching properties for the damaged oxides.

Abstract: The process in which anhydrous HF (AHF) is mixed with the vapor of an organic solvent for the purpose of etching of native SiO2 on Si surfaces is well established (e.g [1-4]). The process was also explored as part of a dry-wet wafer cleaning sequence [5]. More recently, the same process has been successfully expanded into MEMS technology for the purpose of stiction-free releasing of structures by isotropic etching of sacrificial SiO2 [6,7]. The current strong push in advanced Si digital IC technology toward extremely fragile 3D geometries engraved on Si wafer surfaces, in which case conventional etch methods may not work properly [8], as well as needs with regard to native oxide etching in emerging Si-based technologies such as solar cell manufacturing has brought about renewed interest in AHF technology.

Abstract: In this work, we studied HF/scCO2 dry etching processes with various co-solvents for the purpose of reducing the residues. The effect of co-solvent on etch rate and selectivity was also investigated.

Abstract: As semiconductor technology moves past the 32nm CMOS node, material loss becomes an ever more important topic. Besides impacting the size of physical features, material loss impacts electrical results, process control, and defectivity. The challenge this poses is further exacerbated by the introduction of new materials. The largest single influx of new materials has come over the last decade with the introduction of high-k/metal gate (HK/MG) materials. This paper focuses on the front-end-of-line (FEOL), summarizing key materials loss issues by process loop.

Abstract: High dose, ultra shallow junction implant resist strip requires minimal substrate loss and dopant loss. Silicon recess (silicon loss) under the source/drain (S/D) extensions increases the S/D extension resistance and decreases drive currents by changing the junction profile. ITRS surface preparation technology roadmap [1] targets silicon loss to be 0.4Å per cleaning step for 45nm and 0.3Å for 32nm generation. Fluorine-containing chemistries which are often used to enhance implanted resist strip and residue removal result in unacceptable substrate loss. A non-fluorine plasma strip was developed in earlier work and is qualified for 45nm logic production [2]. The objective of this work is to study the substrate damage that is induced by the resist strip plasma process. Silicon surface oxidation and silicon loss of different plasma strip chemistries were evaluated with various metrologies such as optical ellipsometry, electrical oxide measurement, XPS, TEM and mass measurement. The impact of different strip chemistries on dopant retention and distribution is also discussed.