Ultra Clean Processing of Semiconductor Surfaces IX

Volumes 145-146

doi: 10.4028/www.scientific.net/SSP.145-146

Paper Title Page

Authors: Sabrina Bilouk, Carole Pernel, Lucile Broussous, Valentina Ivanova, Ricardo Nogueira

Abstract: The integration of CoWP and CoWB self-aligned barriers (SAB) for 32 nm technology nodes allows improving copper interconnections reliability...

343
Authors: Maria Heidenblut, D. Sturm, Alfred Lechner, Franz Faupel

Abstract: The subject of this report is the characterization of plasma etch residues after a metal etch process with Cl2/BCl3 etch gases. One of the...

349
Authors: Berthold Ferstl, Andreas Klipp, Manfred Essig, Maria Heidenblut

Abstract: Driven by cost saving pressure and new regulations such as REACH, the imple¬mentation of cost efficient, EHS-friendly alternatives is in...

353
Authors: Cheng Kuen Chen, Pi Chun Yu, Ming Hsiu Lee, Chih Ning Wu, Hiroshi Matsuo

Abstract: The borderless (BDL) vias landing on the metal lines were demanded in high-density flash memory devices due to the reduced die size,...

357
Authors: Yasa Sampurno, Yun Zhuang, Xun Gu, Sian Theng, Takenao Nemoto, Ting Sun, Fransisca Sudargho, Akinobu Teramoto, Ara Philipossian, Tadahiro Ohmi

Abstract: Brush scrubbing has been widely used in post chemical mechanical planarization (CMP) applications to remove contaminations, such as slurry...

363
Authors: Han Chul Cho, Young Min Kim, Hyun Seop Lee, Suk Bae Joo, Hae Do Jeong

Abstract: Cu (copper) has been widely used for interconnection structure in integrated circuits because of its properties such as a low resistivity...

367
Authors: Francesco Pipia, Annamaria Votta, Alice C. Elbaz, Salvo Grasso, Enrica Ravizza, Simona Spadoni, Mauro Alessandri

Abstract: In damascene architecture, widely used both in flash memories and in DRAM as interconnect scheme since 90 nm node, copper surface is exposed...

371
Authors: Dave M. Gage, A.D.W. Thiel, R.H. Dauskardt, M.K. Haas, L.M. Matz, M.L. O'Neill, T.M. Wieder, G. Banerjee, M.B. Rao

Abstract: The development of robust integration processes for low-dielectric-constant materials is critical in order to meet the ITRS timeline. For...

377
Authors: Xun Gu, Takenao Nemoto, Akinobu Teramoto, Rui Hasebe, Takashi Ito, Tadahiro Ohmi

Abstract: As technology node progressing, ultra low-k film has been implemented to reduce RC delay in LSI circuit. A fluorocarbon (CFx) film is...

381
Authors: Jerome Daviot, Jan Vaes

Abstract: At critical dimensions of 65nm and lower, the tolerances for yield impacting “killer” particle defects become ever tighter and this is...

385

Showing 81 to 90 of 91 Paper Titles