Silicon Carbide and Related Materials 2005

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Authors: Lin Cheng, Janna R. B. Casady, Michael S. Mazzola, V. Bondarenko, Robin L. Kelley, Igor Sankin, J. Neil Merrett, Jeff B. Casady
Abstract: In this work we have demonstrated the operation of 600-V class 4H-SiC vertical-channel junction field-effect transistors (VJFETs) with 6.6-ns rise time, 7.6-ns fall time, 4.8-ns turn-on and 5.4-ns turn-off delay time at 2.5 A drain current (IDS), which corresponds to a maximum switching frequency of 41 MHz – the fastest ever reported switching of SiC JFETs to our knowledge. At IDS of 12 A, a 19.1 MHz maximum switching frequency has been also achieved. Specific on-resistance (Rsp-on) in the linear region is 2.5 m·cm2 at VGS of 3 V. The drain current density is greater than 1410 A/cm2 at 9 V drain voltage. High-temperature operation of the 4H-SiC VJFETs has also been investigated at temperatures from 25 °C to 225 °C. Changes in the on-resistance with temperature are in the range of 0.90~1.33%/°C at zero gate bias and IDS of 50 mA. The threshold voltage becomes more negative with a negative shift of 0.096~0.105%/°C with increasing temperature.
Authors: Yu Zhu Li, Petre Alexandrov, Jian Hui Zhang, Larry X. Li, Jian H. Zhao
Abstract: SiC JFET, compared with SiC MOSFET, is attractive for high power, high temperature applications because it is free of gate oxide reliability issues. Trenched-and-Implanted VJFET (TIVJFET) does not require epi-regrowth and is capable of high current density. In this work we demonstrate two trenched-and-implanted normally-off 4H-SiC vertical junction field-effect transistors (TI-VJFET), based on 120μm, 4.9×1014cm-3 and 100μm, 6×1014cm-3 drift layers. The corresponding devices showed blocking voltage (VB) of 11.1kV and specific on-resistance (RSP_ON) of 124m7cm2, and VB of 10kV and RSP_ON of 87m7cm2. A record-high value for VB 2/RSP_ON of 1149MW/cm2 was achieved for normally-off SiC FETs.
Authors: Jian H. Zhao, Petre Alexandrov, Yu Zhu Li, Larry X. Li, Kuang Sheng, Ramon Lebron-Velilla
Abstract: This paper reports recent progress in the development of a vertical JFET, the purely vertical JFET based on trenched-and-implanted vertical JFET (TI-VJFET) approach that eliminates the need of epitaxial regrowth at middle of device fabrication and the need of a merged lateral JFET to control the vertical JFET. Different structures have been designed to target breakdown voltages ranging from 600V to 1.2kV. Vertical channel width uniformity has been studied, showing the feasibility of achieving below 0.1um variation for reasonably flat wafers of good thickness uniformity. Pitch size of the designs has been reduced compared to early report. Gate trench width has been reduced from 3.8um to 2.3um, aimed at increasing the device current capability. Fabricated device cells have been tested and packaged into multi-cell 30A TI-VJFETs which have been characterized of DC and switching characteristics at room and elevated temperatures. Very fast current rise/fall times of <10ns were observed from RT to 200°C. PSpice model for TI-VJFET has been developed and applied to the performance prediction of 3-phase SiC power inverter, suggesting a high efficiency 97.7% at 200°C junction temperature without using soft-switching scheme. Preliminary experimental demonstration of a PWM-controlled three-phase inverter based on SiC TI-VJFET power board is reported.
Authors: Praneet Bhatnagar, Alton B. Horsfall, Nicolas G. Wright, C. Mark Johnson, Konstantin Vassilevski, Anthony G. O'Neill
Abstract: Physics-based analytical models are seen as an efficient way of predicting the characteristics of power devices since they can achieve high computational efficiency and may be easily calibrated using parameters obtained from experimental data. This paper presents an analytical model for a 4H-SiC Enhancement Mode Vertical JFET (VJFET), based on the physics of this device. The on-state and blocking behaviour of VJFETs with finger widths ranging from 1.6+m to 2.2+m are studied and compared with the results of finite element simulations. It is shown that the analytical model is capable of accurately predicting both the on-state and blocking characteristics from a single set of parameters, underlining its utility as a device design and circuit analysis tool.
Authors: Y.C. Choi, Ho Young Cha, Lester F. Eastman, Michael G. Spencer
Abstract: A new silicon carbide (SiC) enhancement-mode lateral channel vertical junction fieldeffect transistor (LC-VJFET), namely “source inserted double-gate structure (SID-gate) with a supplementary highly doped region (SHDR)”, was proposed for achieving extremely low power losses in high power switching applications. The proposed architecture was based on the combination of an additional source electrode inserted between two adjacent surface gate electrodes and a unique SHDR in the vertical channel region. Two-dimensional numerical simulations for the static and resistive switching characteristics were performed to analyze and optimize the SiC LCVJFET structures for this purpose. Based on the simulation results, the excellent performance of the proposed structure was compared with optimized conventional structures with regard to total power losses. Finally, the proposed structure showed about a 20 % reduction in on-state loss (Pon) compared to the conventional structures, due to the effective suppression of the JFET effect. Furthermore, the switching loss (Psw) of the proposed structure was found to be much lower than the results of the conventional structures, about a 75 % ~ 95 % reduction, by significantly reducing both input capacitance (Ciss) and reverse transfer capacitance (Crss) of the device.
Authors: Takeyoshi Masuda, Kazuhiro Fujikawa, Kaoru Shibata, Hideto Tamaso, Satoshi Hatsukawa, Hitoki Tokuda, Akihiko Saegusa, Yasuo Namikawa, Hideki Hayashi
Abstract: We fabricated 4H-SiC lateral JFETs with a reduced surface field (RESURF) structure, which can prevent the concentration of electric field at the edge of the gate metal [1]. Previously, we reported on the 4H-SiC RESURF JFET with a gate length (LG) of 10 μm [2]. Its specific on-resistance was 50 mΩcm2, which was still high. Therefore, a Ti/W layer was used as an ion implantation mask so as to decrease the thickness of the mask and to improve an accuracy of the device process. A RESURF JFET with the gate length (LG) of 3.0 μm was fabricated, and the specific on-resistance of 6.3 mΩcm2 was obtained. In this paper, the fabrication process and the electrical characteristics of the device are described.
Authors: Igor Sankin, V. Bondarenko, Robin L. Kelley, Jeff B. Casady
Abstract: Wide bandgap semiconductor materials such as SiC or GaN are very attractive for use in high-power, high-temperature, and/or radiation resistant electronics. Monolithic or hybrid integration of a power transistor and control circuitry in a single or multi-chip wide bandgap power semiconductor module is highly desirable for such applications in order to improve the efficiency and reliability. This paper describes a new monolithic SiC JFET IC technology for high-temperature smart power applications that allows for on-chip integration of control circuitry and normally-off power switch. In order to demonstrate the feasibility of this technology, hybrid logic gates with maximum switching frequency > 20 MHz and normally-off 900 V power switch have been fabricated on alumina substrates using discrete enhanced and depletion mode vertical trench JFETs.
Authors: Robin L. Kelley, T. Brignac, Michael S. Mazzola, Jeff B. Casady
Abstract: The power junction field effect transistor (JFET) is the second most mature SiC device, after the SiC Schottky diode, and is commonly associated with normally on functionality; but this feature is often viewed problematically for off-line dc-to-dc converter applications. Two inherently safe, single-switch dc-dc converter designs have been developed that put into practice pure SiC JFET devices (i.e., without cascoded devices) that possess enhancement-mode functionality and bias-enhanced blocking. These ‘Quasi-Off’ devices are designed to block half of the rated blocking voltage at zero gate bias and achieve full rated blocking voltage with a modest negative bias, typically between 0 and -5 V. Inherent safety is provided by utilizing the enhancement mode functionality of these devices as well as appropriate gate driver design. Bias enhanced blocking matches the dynamic stress encountered by modern high-frequency power supply topologies to the ratings of the device while recognizing that the larger dynamic stress is typically encountered only when the power supply (and especially the gate driver) is functioning properly.
Authors: Dominique Tournier, Miquel Vellvehi, Phillippe Godignon, Josep Montserrat, Dominique Planson, F. Sarrus
Abstract: High voltage, high current capabilities of SiC based devices has been already proved, and high current SiC devices working at high temperature are likely to be on the market soon. SiC power integration will have to be considered as a further development step to discrete power devices. Packaging and device integrated protections remain the main constraints for high temperature operation and system integration. In case of short-circuit or over-current, SiC devices can reach high temperature values, and the die might be subjected to high stresses. In order to address such critical requirements, current sensing and real time temperature monitoring are mandatory. The structure proposed in this paper, derived from Si technology, provides a protection feature to SiC power devices to get reliable high temperature electronics. Concretely, an integrated current sensor has been implemented in a vertical power SiC JFET and its fabrication is reported for the first time. The current sensor layout and process technology are presented. An experimental current sensing validation is also reported.
Authors: Yasunori Tanaka, Koji Yano, Mitsuo Okamoto, Akio Takatsuka, Kenji Fukuda, Masanobu Kasuga, Kazuo Arai, Tsutomu Yatsuo
Abstract: Silicon carbide static induction transistors with submicron buried p+ gate (SiC-BGSITs) have been successfully developed through innovative fabrication process. A submicron buried p+ gate structure was fabricated by the combination of submicron trench dry etching and epitaxial growth process on a trench structure. As the device performance is mainly determined by the width of the p+ gate region and the spacing between two adjacent p+ gate regions, corresponding to the width of n- channel, we have optimized these parameters carefully using a device simulator. The breakdown voltage VBR and specific on-resistance RonS of the fabricated BGSIT were 700 V at a gate voltage VG = –12 V and 1.01 m/·cm2 at VG = 2.5 V and a drain current density JD = 200 A/cm2, respectively. This RonS is the lowest on-resistance for ~ 600V class power switching devices, including other wide-bandgap materials such as GaN.

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