Silicon Carbide and Related Materials 2005

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Authors: Masato Noborio, Yuki Negoro, Jun Suda, Tsunenobu Kimoto
Abstract: SiC lateral MOSFETs with multi-RESURF structures have been fabricated by a self-aligned process. The “multi-RESURF” means “double RESURF” and “buried-p RESURF” structures, which have the buried-p region at the top and at the middle of RESURF region, respectively. The increase of net RESURF dose and the decrease of channel length lead to the reduced on-resistance. The “buried-p RESURF” MOSFETs have higher on-resistances than the “double RESURF” MOSFETs, due to the resistance of parasitic JFET inside the RESURF region. The dose designing for double RESURF MOSFETs has been optimized by using device simulation. A double RESURF MOSFET exhibits a breakdown voltage of 750 V and an on-resistance of 52 m/cm2.
Authors: Ryouji Kosugi, Kenji Suzuki, Kazuto Takao, Yusuke Hayashi, Tsutomu Yatsuo, Kenji Fukuda, Hiromichi Ohashi, Kazuo Arai
Abstract: A passivation annealing in nitric oxide (NO) ambient significantly reduces the interfacial defects of the SiO2/4H-SiC interface and improves the inversion MOS channel mobility. Effects of the nitridation in NO ambient become more pronounced at high temperatures in general. However, the maximum process temperature in a standard hot-wall oxidation furnace is restricted around 1200oC due to the softening point of quartz. Meanwhile, by use of a cold-wall oxidation furnace, high temperature and short time thermal processes become possible. In this study, we have developed an extremely high temperature (>1400oC) rapid thermal processing for the gate oxidation in the 4H-SiC DIMOSFET fabrication process. The peak MOS channel mobility of lateral MOSFETs on the DIMOSFET chip shows as high as 19cm2/Vs. The specific on-resistance of the device was 12.5mcm2 and the blocking voltage was 950V with gate shorted to the source.
Authors: Sumi Krishnaswami, Sei Hyung Ryu, Bradley Heath, Anant K. Agarwal, John W. Palmour, Bruce Geil, Aivars J. Lelis, Charles Scozzie
Abstract: Gate oxide reliability measurements of 4H-SiC DMOSFETs were performed using the Time Dependent Dielectric Breakdown (TDDB) technique at 175°C. The oxide lifetime is then plotted as a function of the electric field. The results show the projected oxide lifetime to be > 100 years at an operating field of ~3 MV/cm. Device reliability of 2.0 kV DMOSFETs was studied by stressing the gate with a constant gate voltage of +15 V at a temperature of 175°C, and monitoring the forward I-V characteristics and threshold voltage for device stability. Our very first measurements show very little variation between the pre-stress and post-stress conditions up to 1000 hrs of operation at 175°C. In addition, forward on-current stressing of the MOSFETs show the devices to be stable up to 1000 hrs of operation.
Authors: Aivars J. Lelis, Daniel B. Habersat, G. Lopez, J.M. McGarrity, F. Barry McLean, Neil Goldsman
Abstract: We have observed instability in the threshold voltage, VT, of SiC metal-oxide semiconductor field-effect transistors (MOSFETs) due to gate-bias stressing. This effect has routinely been observed by us in all 4H and 6H SiC MOSFETs from three different manufacturers—even at room temperature. A positive-bias stress, applying an electric field of about 1 to 2 MV/cm across the gate oxide, for 3 minutes followed by a negative-bias stress for another 3 minutes typically results in a shift of the ID-VGS current-voltage characteristic in the range of 0.25 to 0.5 V and is repeatable. We speculate that this effect is due to the presence of a large number of near-interfacial oxide traps that presumably lie in the oxide transition region that extends several nm into the oxide from the SiC interface, caused by the presence of C and strained SiO2. This instability is consistent with charge tunneling in and out of these near-interfacial oxide traps, which in irradiated Si MOSFETs has been attributed to border traps. Also consistent with charge tunneling is the observed linear increase in the magnitude of the SiC VT instability with log (time).
Authors: Siddharth Potbhare, Gary Pennington, Neil Goldsman, Aivars J. Lelis, Daniel B. Habersat, F. Barry McLean, J.M. McGarrity
Abstract: A physics based device simulator for detailed numerical analysis of 4H-SiC MOSFETs with an advanced mobility model that accounts for the effects of bulk and surface phonons, surface roughness and Coulomb scattering by occupied interface traps and fixed oxide charges, has been developed. A first principles quasi-2D Coulomb scattering mobility model specifically for SiC MOSFETs has been formulated. Using this, we have been able to extract the interface trap density of states profile for 4H-SiC MOSFETs and have shown that at room temperature, Coulomb scattering controls the total mobility close to the interface. High temperature, low field simulations and experiments show that the current increases with increase in temperature. The effect of Coulomb scattering decreases with increase in temperature causing an increase in the total mobility near the interface at low gate voltages.
Authors: Alton B. Horsfall, C.H.A. Prentice, Peter Tappin, Praneet Bhatnagar, Nicolas G. Wright, Konstantin Vassilevski, Irina P. Nikitina
Abstract: Although Silicon Carbide has become the material of choice for high power applications in a range of extreme environments, the interest in creating active chemical sensors requires the development of transistors for additional control circuits to operate in these environments. Despite the recent advances in the quality of oxide layers on SiC, the mobility of inversion layers is still low and this will affect the maximum frequency of the operation for these devices. We present simulation results which indicate that a delta channel, in both n-channel and p-channel structures, is suitable for transistors used with these low level signals. By varying the doping levels of the device we have shown that the optimum delta doping for this application is 1.43x1019 cm-3 for both n and p channel devices. We then show the effects of high temperatures on the delta FET devices and make comparisons with standard SiC MOSFET devices.
Authors: Mrinal K. Das, Joseph J. Sumakeris, Brett A. Hull, Jim Richmond
Abstract: The PiN diode is an attractive device to exploit the high power material advantages of 4H-SiC. The combination of high critical field and adequate minority carrier lifetime has enabled devices that block up to 20 kV and carry 25 A. Furthermore, these devices exhibit fast switching with less reverse recovery charge than commercially available Si PiN diodes. The path to commercialization of the 4H-SiC PiN diode technology, however, has been hampered by a fundamental problem with the forward voltage stability resulting from stacking fault growth emanating from basal plane screw dislocations (BPD). In this contribution, we highlight the progress toward producing stable high power devices with sufficient yield to promote commercial interest. Two independent processes, LBPD1 and LBPD2, have been shown to be effective in reducing the BPD density and enhancing the forward voltage stability while being compatible with conventional power device fabrication. Applying the LBPD1 and LBPD2 processes to 10 kV (20 A and 50 A) 4H-SiC PiN diode technology has resulted in a dramatic improvement in the total device yield (forward, reverse, and forward drift yields) from 0% to >20%. The LBPD1 process appears to be more robust in terms of long term forward voltage stability.
Authors: Philip G. Neudeck, David J. Spry, Andrew J. Trunek
Abstract: This paper reports on initial fabrication and electrical characterization of 3C-SiC p+n junction diodes grown on step-free 4H-SiC mesas. Diodes with n-blocking-layer doping ranging from ~ 2 x 1016 cm-3 to ~ 5 x 1017 cm-3 were fabricated and tested. No optimization of junction edge termination or ohmic contacts was employed. Room temperature reverse characteristics of the best devices show excellent low-leakage behavior, below previous 3C-SiC devices produced by other growth techniques, until the onset of a sharp breakdown knee. The resulting estimated breakdown field of 3C-SiC is at least twice the breakdown field of silicon, but is only around half the breakdown field of <0001> 4H-SiC for the doping range studied. Initial high current stressing of 3C diodes at 100 A/cm2 for more than 20 hours resulted in less than 50 mV change in ~ 3 V forward voltage.
Authors: Michael E. Levinshtein, Pavel A. Ivanov, Mykola S. Boltovets, Valentyn A. Krivutsa, John W. Palmour, Mrinal K. Das, Brett A. Hull
Abstract: Steady-state and transient characteristics of packaged 6-kV 4H-SiC junction diodes have been investigated in the temperature range Т = 300 – 773 К. Analysis of the forward current-voltage characteristics and reverse current recovery waveforms shows that the lifetimeτ of non-equilibrium carriers in the base of the diodes steadily increases with temperature across the entire temperature interval. The rise in τ and decrease in carrier mobilities and diffusion coefficients with increasing temperature nearly compensate each other as regards their effect on the differential resistance of the diode, Rd. As a result, Rd is virtually temperature independent. An appreciable modulation of the base resistance takes place at room temperature even at a relatively small current density j of 20 A/cm2. At T = 800 K and j = 20 A/cm2, a very deep level of the base modulation has been observed. The bulk reverse current is governed by carrier generation in the space-charge region via a trap with activation energy of 1.62 eV. The surface leakage current of packaged structures does not exceed 2×10-6 А at T = 773 K and a reverse bias of 300 V.
Authors: Anatoly M. Strel'chuk, A.V. Mashichev, Alexander A. Lebedev, A.N. Volkova, Konstantinos Zekentes
Abstract: The forward current was investigated in 4H-SiC p+n structures grown by sublimation epitaxy. The doping level, Nd-Na, of the n-layer was about (3-4)x1016 cm-3 and the diode area was in the range from 1x10-5 to 2x10-4 cm2. The observed current can be considered as current due to bulk recombination in the space charge region of the pn junction via deep level center or due to surface recombination. The criterion which was performed in this study to differentiate such currents was the investigation of recombination current versus perimeter/area ratio dependence. It was found that no pronounced difference in the recombination current parameters for diodes with different perimeter/area ratio was observed, i.e. current due to surface recombination was not observed for the 4H-SiC pn structures investigated.

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