Silicon Carbide and Related Materials 2005

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Authors: J. Neil Merrett, Igor Sankin, V. Bondarenko, C.E. Smith, D. Kajfez, Janna R. B. Casady
Abstract: Trenched, vertical SiC static induction transistors (SIT) for L-band power amplification were fabricated with implanted p-n junction gates on conducting n-type 4H-SiC substrates using a self-aligned fabrication process. The self-aligned fabrication process required no critical alignments and allowed for high channel packing densities ranging from 2.9x103 to 5x103 cm/cm2. Devices were fabricated with a range of finger widths. Devices with the narrowest fingers were able to block up to 450 V with VGS = -3 V. Devices with wider fingers required higher gate voltages ranging from -10 V to -25 V to achieve similar blocking. Devices were packaged and small-signal and loadpull measurements were taken with the devices externally matched. Devices having the narrowest finger design had a small-signal power gain of over 9 dB at around 1.3 GHz. Load-pull measurements of packaged SITs with 1 cm gate periphery yielded a maximum power gain of ~ 8.2 dB at 1 GHz, VDD = 100 V, and VGS = 1.2 V. Due to the high packing density, these results translate to power densities of 22 kW/cm2.
1223
Authors: Per Åke Nilsson, Niklas Rorsman, Mattias Südow, Kristoffer Andersson, Hans Hjelmgren, Herbert Zirath
Abstract: In order to increase the output power and drain efficiency, MESFETs in SiC have been made with a double gate recess technique. Typical device characteristics of the MESFETs are drain currents of 380mA/mm, breakdown voltages of 80V and ft/fmax of 10/25 GHz respectively. These transistors exhibit power densities of 3W/mm@3GHz in class AB operation and drain efficiencies of 60%. Packaged devices with 3 mm gate periphery of this type, with via-hole grounding, gave power densities of 1.2 W/mm@6GHz at 50 V drain bias.
1227
Authors: Andrey O. Konstantinov, J.O. Svedberg, I.C. Ray, Chris I. Harris, Christer Hallin, B.O. Larsson
Abstract: High power high efficiency silicon carbide RF MESFETs are fabricated using a novel structure utilizing lateral epitaxy. The MESFET employs buried p-type depletion stoppers grown by lateral epitaxy with subsequent planarization. The depletion stopper is epitaxially overgrown by the channel layer. The depletion stopper suppresses short channel effects and increases the operation voltage and the RF signal gain at high voltage operation. High breakdown voltages of over 200 Volts are achieved for single-cell components, however large-area transistors are limited to around 150 Volts. Single-cell components measured on-wafer demonstrate an Ft of 10 GHz and high unilateral gain. Packaged 6-mm RF transistors in amplifier circuits feature a saturated power of 20 W and a P1dB of 15W with a linear gain of over 16 dB at Vdd of 60 V for 2.25 GHz operation. Maximum drain efficiency is 56% for class AB operation, 48% at 1 dB compression point and 72% for class C at 2.25 GHz.
1231
Authors: Makoto Ogata, S. Katakami, Shuichi Ono, Manabu Arai
Abstract: We fabricated a 0.5-μm gate MESFET on a bulk semi-insulating 4H-SiC substrate by using ion implantation for the channel layer and contact region. Nitrogen ions were implanted to obtain a 0.25-μm-thick box-shaped profile with a doping density of 3.0×1017/cm3 for the channel region and to obtain a 0.2-μm-thick box-shaped profile with a doping density of 2.0×1020/cm3 for the contact region. Activation annealing is done in argon ambient at 1300 °C for 30 minutes. A 0.5- μm gate MESFET with 100-μm gate width showed a cut-off frequency of 7.5 GHz and a maximum oscillation frequency of 22.2 GHz. And its saturated output power was 25 dBm (3.16 W/mm), power gain was 6.7 dB and PAE was 15.7%.
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Authors: Kevin Matocha, Ed Kaminsky, Alexey Vertiatchikh, Jeff B. Casady
Abstract: 4H-SiC MESFETs were fabricated using a bilayer dry thermal oxide/low-pressure chemical vapor deposited (LPCVD) silicon nitride for surface passivation. The passivation dielectric consists of a 20 nm thick dry thermal oxide covered by a 45 nm thick LPCVD silicon nitride layer. Devices utilize a recessed-channel architecture with 0.6 micron T-gates. Devices with the bilayer SiO2/SiNx passivation achieved a ft=9.3 GHz and fmax=15.5 GHz (WG=1.5 mm). The device transconductance was 34 mS/mm, drain current density was 235 mA/mm, and pinchoff voltage was –8V. Devices were load-pull characterized at 3 GHz with a 10% duty cycle and 100 μs repetition rate and a Class AB quiescent bias of IDS=100 mA/mm, and VDS=30V. Large devices with a 9.6 mm gate-periphery deliver an output power of 43.2 dBm (20.9 W=2.2W/mm) with a power-added-efficiency of 59% at a gain of 8.8 dB.
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Authors: Dominique Tournier, Miquel Vellvehi, Phillippe Godignon, Xavier Jordá, José Millan
Abstract: The potential of SiC MESFETs has been demonstrated for high frequency applications on several circuits in the 1-5 GHz frequency range. Although MESFET structures are conventionally used for RF applications, in this paper we report a low voltage (180V) power switch and its current limiting application based on a double gate MESFET structure, showing enhanced forward and blocking capabilities. The reported devices utilize a thin highly doped p-type layer implanted at high energy as buffer layer. Various layouts have been fabricated, varying the gate length; with either a single gate (p-buried layer connected to source) or double gate (one Schottky, and the second on the P-buried layer). Gate RESURF field-plate variation has been also included at the gate electrode. The I(V) electrical characterization validates the double gate configuration benefits. This double gate structure shows a higher gate transconductance than the single gate one. High voltage measurements in conducting mode (180V, 160mA/mm, 30W/mm) confirm the operation of the MESFET as a current limiting device, with excellent gate control capabilities at temperature up to 190°C.
1243
Authors: Mohamed Trabelsi, Nabil Sghaier, Jean Marie Bluet, Noureddine Yacoubi, Gérard Guillot, Christian Brylinski
Abstract: Our work is focused on the identification of defects responsible for current fluctuations at the origin of low frequency noise or random telegraphic signals in 4H-SiC MESFETs on semiinsulating (SI) substrates. We show that devices having instabilities have DC output characteristics with random discrete fluctuations of the drain current. The RTS noise parameters analysis (amplitude, high and low state time durations) as a function of temperature and bias voltage provides the signature of the involved traps (activation energy and cross section both for emission and capture). From the power spectral density of the drain current noise (PSD) we have measured the cut-off frequency of a single trap even at very low frequencies (from 0.1 Hz) and we propose that the noise responsible of RTS fluctuations is a generation-recombination noise. Finally, it is shown that the frequency analysis of the random telegraphic signal is a well-suited tool for the study of single defects in very small devices.
1251
Authors: Dethard Peters, Reinhold Schörner, Peter Friedrichs, Dietrich Stephani
Abstract: SiC power MOSFETs are attractive electronic power switches for innovative power supply and motor drive solutions. The paper discusses this statement and specifies market segments offering the best chances for a commercialization. Due to well-known difficulties in achieving adequate channel conductivity, a lot of SiC-MOSFET publications focus on the channel mobility. However, for a power MOSFET this is only one important parameter affecting the performance. Other characteristics have to be considered too for an honest evaluation: transfer characteristics and blocking capability over the standard operation temperature range, handling of gate oxide stress and related reliability issues, capability of paralleling, dynamic stability, body diode characteristics, reproducibility of the fabrication process and device size. Various attempts have been made in recent years in order to address these features. Approaches differ in the use of different crystal orientations and polytypes, accumulation or inversion channel, implanted or epitaxially grown channels and novel oxidation techniques. Worldwide a trend to the planar DIMOS concept can be observed. Our present results are shown for a power SiC MOSFET designed for 10 A / 1200 V. Key data are a specific on-resistance of 12 m1cm2, the desired low but positive increase of the onresistance with temperature, static avalanche (20 mA DC @1574 V), short-circuit stability at 600 V for 20 9s and robust switching behavior.
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Authors: Sei Hyung Ryu, Sumi Krishnaswami, Brett A. Hull, Bradley Heath, Mrinal K. Das, Jim Richmond, Anant K. Agarwal, John W. Palmour, James D. Scofield
Abstract: 8 mΩ-cm2, 1.8 kV power DMOSFETs in 4H-SiC are presented in this paper. A 0.5 μm long MOS gate length was used to minimize the MOS channel resistance. The DMOSFETs were able to block 1.8 kV with the gate shorted to the source. At room temperature, a specific onresistance of 8 mΩ-cm2 was measured with a gate bias of 15 V. At 150 oC, the specific onresistance increased to 9.6 mΩ-cm2. The increase in drift layer resistance due to a decrease in bulk electron mobility was partly cancelled out by the negative shift in MOS threshold voltage at elevated temperatures. The device demonstrated extremely fast, low loss switching characteristics. A significant improvement in converter efficiency was observed when the 4H-SiC DMOSFET was used instead of an 800 V silicon superjunction MOSFET in a simple boost converter configuration.
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