Silicon Carbide and Related Materials 2005

Paper Title Page

Authors: Jeffery B. Fedison, Chris S. Cowen, Jerome L. Garrett, E.T. Downey, James W. Kretchmer, R.L. Klinger, H.C. Peters, Jesse B. Tucker, Kevin Matocha, L.B. Rowland, Steve Arthur
Abstract: Results of a 1200V 4H-SiC vertical DMOSFET based on ion implanted n+ source and pwell regions are reported. The implanted regions are activated by way of a high temperature anneal (1675°C for 30 min) during which the SiC surface is protected by a layer of graphite. Atomic force microscopy shows the graphite to effectively prevent surface roughening that otherwise occurs when no capping layer is used. MOSFETs are demonstrated using the graphite capped anneal process with a gate oxide grown in N2O and show specific on-resistance of 64 mW×cm2, blocking voltage of up to 1600V and leakage current of 0.5–3 ´10-6 A/cm2 at 1200V. The effective nchannel mobility was found to be 1.5 cm2/V×s at room temperature and increases as temperature increases (2.8 cm2/V×s at 200°C).
Authors: Asmita Saha, James A. Cooper
Abstract: We describe an optimized design for the 1 kV short-channel 4H-SiC power DMOSFET, obtained from numerical simulations using the Taguchi method. Three new structural features are employed: (1) a current spreading layer (CSL) below the p-well, (2) a heavily-doped, narrow JFET region, and (3) a segmented p-well contact.
Authors: Adolf Schöner, Mietek Bakowski, Per Ericsson, Helena Strömberg, Hiroyuki Nagasawa, Masayuki Abe
Abstract: Vertical DMOSFET devices with varying size from single cell to 3x3 mm2 large devices have been realized. The investigated devices had hexagonal and square unit cell designs with 2 $m and 4 $m channel length. The p-body was aluminum implanted and the source was nitrogen or phosphorus implanted. Low temperature Ti/W contacts were evaluated.
Authors: G. Gudjónsson, Fredrik Allerstam, H.Ö. Ólafsson, Per Åke Nilsson, Hans Hjelmgren, Kristoffer Andersson, Einar Ö. Sveinbjörnsson, Herbert Zirath, T. Rödle, R. Jos
Abstract: We have made a 4H-SiC RF power MOSFETs with cutoff frequency up to 12 GHz, delivering RF power of 1.9 W/mm at 3 GHz. The transistors withstand 200 V drain voltage, are normally-off, and show no gate lag, which is often encountered in SiC MESFETs. The measured devices have a single drain finger and a double gate finger and a total gate width of 0.8 mm. To our knowledge this is the first time that power densities above 1 W/mm at 3 GHz are reported for SiC MOSFETs.
Authors: Shinsuke Harada, Makoto Kato, Mitsuo Okamoto, Tsutomu Yatsuo, Kenji Fukuda, Kazuo Arai
Abstract: The channel mobility in the SiC MOSFET degrades on the rough surface of the p-well formed by ion implantation. Recently, we have developed a double-epitaxial MOSFET (DEMOSFET), in which the p-well comprises two stacked epitaxially grown p-type layers and an n-type region between the p-wells is formed by ion implantation. This device exhibited a low on-resistance of 8.5 mcm2 with a blocking voltage of 600 V. In this study, to further improve the performance, we newly developed a device structure named implantation and epitaxial MOSFET (IEMOSFET). In this device, the p-well is formed by selective high-concentration p+ implantation followed by low-concentration p- epitaxial growth. The fabricated IEMOSFET with a buried channel exhibited superior characteristics to the DEMOSFET. The extremely low specific on-resistance of 4.3 mcm2 was achieved with a blocking voltage of 1100 V. This value is the lowest in the normally-off SiC MOSFETs.
Authors: Yoichiro Tarui, Tomokatsu Watanabe, Keiko Fujihira, Naruhisa Miura, Yukiyasu Nakao, Masayuki Imaizumi, Hiroaki Sumitani, Tetsuya Takami, Tatsuo Ozeki, Tatsuo Oomori
Abstract: 4H-SiC epilayer channel MOSFETs are fabricated. The MOSFETs have an n- epilayer channel which improves the surface where the MOS channel is formed. By the optimization of the epilayer channel and the MOSFET cell structure, an ON-resistance of 12.9 mcm2 is obtained at VG = 12 V (Eox = 2.9 MV/cm). A normally-OFF operation and stable avalanche breakdown is obtained at the drain voltage larger than 1.2 kV. Both the ON-resistance and the breakdown voltage increase slightly with an increase in temperature. This behavior is favorable for high power operation. By the evaluation of the control MOSFETs with n+ implanted channel, the resistivity of the MOS channel is estimated. The MOS channel resistivity is proportional to the channel length and it corresponds to an effective channel mobility of about 20 cm2/Vs.
Authors: Masayuki Imaizumi, Yoichiro Tarui, Shin Ichi Kinouchi, Hiroshi Nakatake, Yukiyasu Nakao, Tomokatsu Watanabe, Keiko Fujihira, Naruhisa Miura, Tetsuya Takami, Tatsuo Ozeki
Abstract: Prototype SiC power modules are fabricated using our class 10 A, 1.2 kV SiC-MOSFETs and SiC-SBDs, and their switching characteristics are evaluated using a double pulse method. Switching waveforms show that both overshoot and tail current, which induce power losses, are suppressed markedly compared with conventional Si-IGBT modules with similar ratings. The total switching loss (MOSFET turn-ON loss, turn-OFF loss and SBD recovery loss) of SiC power modules is measured to be about 30% of that of Si-IGBT modules under the generally-used switching condition (di/dt ~250A/μs). The three losses of SiC modules decrease monotonically with a decrease in gate resistance, namely switching speed. The result shows the potential of unipolar device SiC power modules.
Authors: H. Nakao, Hideno Mikami, Hiroshi Yano, Tomoaki Hatayama, Yukiharu Uraoka, Takashi Fuyuki
Authors: Hiroyuki Fujisawa, Takashi Tsuji, Masaharu Nishiura
Abstract: This paper reports the channel mobilities of MOSFETs formed on the trench sidewalls with different crystal faces including (0001), (000-1), (1-100) and (0-33-8) using 4H-SiC (11-20) substrates. Deposited poly-Si was oxidized in wet ambient to form the gate oxide, and annealed in N2O (10%) ambient. The order of drain current of trench sidewall MOSFETs was (0-33-8) > (1-100) > (000-1) = (0001). We could gain comparatively high channel mobility on the (0-33-8) face. The maximum effective channel mobility (μeff) was 35cm2/Vs, and μeff at 2.5MV/cm was 29 cm2/Vs on the (0-33-8) face.
Authors: Mitsuo Okamoto, Mieko Tanaka, Tsutomu Yatsuo, Kenji Fukuda
Abstract: We have fabricated inversion-type p-channel MOSFETs on 4H-SiC substrates. In this paper, influences of gate oxidation process on the properties of p-channel MOSFETs were investigated. The gate oxide was formed under these three conditions: (i) dry oxidation, (ii) dry oxidation following wet re-oxidation, and (iii) wet oxidation. The C-V measurements of p-type 4H-SiC MOS capacitors revealed that wet oxidation process reduced the interface states near the valence band. The p-channel MOSFET with low interface states near the valence band indicated low threshold voltage (Vth), high field effect channel mobility (μFE) and low subthreshold swing (S). We obtained 4H-SiC p-channel MOSFET with high μFE of 15.6cm2/Vs by using wet oxidation as gate oxidation process.

Showing 301 to 310 of 379 Paper Titles