Silicon Carbide and Related Materials 2005

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Authors: Gary Pennington, Siddharth Potbhare, Neil Goldsman, Daniel B. Habersat, Aivars J. Lelis
Abstract: In this work we present a comparison between the field-effect (FE) and conductivity (inv) mobilities calculated from ID-VG measurements on a 4H-SiC MOSFET. A compact device model is used to determine inv. The conductivity mobility is found to be larger than FE near room temperature, but less than FE at 500K. These results are due to a reduction in charge trapping at higher temperatures. In strong inversion, inv decreases markedly with increasing temperature. Modeling indicates that surface phonon scattering dominates in this regime.
Authors: Amador Pérez-Tomás, Miquel Vellvehi, Narcis Mestres, José Millan, P. Vennegues, J. Stoemenos
Abstract: A high field-effect mobility peak (50 cm2/Vs) has been extracted in (0001) Si face 4HSiC MOSFETs with oxidized Ta2Si (O-Ta2Si) high-k dielectric (k~20) as gate insulator, with their gates in the strong inversion regime. The interface state density (Dit) has not been particularly reduced in O-Ta2Si capacitors. This anomalous mobility enhancement is explained in terms of Coulomb scattering reduction and quantified using a physical model based on the Lombardi mobility model. The anomalous mobility increase is closely related to the leakage current, and also to the gate breakdown mechanism. We propose a model for which the observed interfacial SiO2 tunnel current combined with Poole-Frenkel mechanisms at the O-Ta2Si gate generates a sufficiently low abrupt transition in gate breakdown to obtain an effective passivation of the interface traps. Under these conditions, the increase of free carriers in the inversion layer induced by the gate leakage diminishes the effect of the interface trap Coulomb scattering.
Authors: Ayayi Claude Ahyi, S.R. Wang, John R. Williams
Abstract: The effects of gamma radiation on field effect mobility and threshold voltage have been studied for lateral n-channel 4H-SiC MOSFETs passivated with nitric oxide. MOS capacitors (n and p) and n-channel lateral MOSFETs were irradiated unbiased (floating contacts) for a total gamma dose of 6.8Mrad (Si). The MOS capacitors were used to study the radiation-induced interface traps and fixed oxide charge that affect the performance of the MOSFETs. Radiationinduced interface traps were observed near the SiC valence band edge and just above mid-gap, and field effect channel mobility was reduced by 18-20% following irradiation. Even so, 4HMOSFETs appear to be more radiation tolerant than Si devices.
Authors: Marc Avice, Ulrike Grossner, Ola Nilsen, Jens S. Christensen, Helmer Fjellvåg, Bengt Gunnar Svensson
Abstract: Al2O3 has been grown by Atomic Layer Chemical Vapour Deposition (ALCVD) on ntype 4H-SiC using O3 as an oxidant. After post-deposition, annealing at high temperature (1000°C) in Argon atmosphere for different time periods (1h, 2h, 3h) was performed. Bulk and interface properties of the as-grown as well as the annealed films were studied by electrical measurements (CV, IV, DLTS) and Secondary Ion Mass Spectrometry (SIMS) measurements. The electrical measurements show a decreasing shift of the flatband voltage indicating a diminution of the negative oxide charges with increasing annealing time. After annealing at 1000°C for 3h, the flatband voltage shift has decreased to 6V. The SIMS measurements indicate a double interface with a SiOx (x ≤ 2) interlayer in the as-grown samples while only one interface is observed after annealing, leading to improved electrical behavior of the Metal-Oxide-Semiconductor devices.
Authors: Carey M. Tanner, Jong Woo Choi, Jane P. Chang
Abstract: The electronic properties of HfO2 films on 4H-SiC were investigated to determine their suitability as high-κ dielectrics in SiC power MOS devices. The band alignment at the HfO2/4HSiC interface was determined by X-ray photoelectron spectroscopy (XPS) and supported by density functional theory (DFT) calculations. For the experimental study, HfO2 films were deposited on ntype 4H-SiC by atomic layer deposition (ALD). XPS analysis yielded valence and conduction band offsets of 1.69 eV and 0.75 eV, respectively. DFT predictions based on two monoclinic HfO2/4HSiC (0001) structures agree well with this result. The small conduction band offset suggests the potential need for further interface engineering and/or a buffer layer to minimize electron injection into the gate oxide.
Authors: Carey M. Tanner, Jun Lu, Hans Olof Blom, Jane P. Chang
Abstract: The material properties of HfO2 thin films were studied to evaluate their potential as a high-κ gate dielectric in 4H-SiC power metal-oxide-semiconductor field effect transistors. Stoichiometric HfO2 films were deposited on n-type 4H-SiC (0001) by atomic layer deposition (ALD) at substrate temperatures of 250-450°C. No significant interfacial layer formation was observed by in-situ X-ray photoelectron spectroscopy (XPS) and an abrupt interface was confirmed by high-resolution transmission electron microscopy (HRTEM). A temperature-dependent transition from amorphous layer-by-layer growth to crystalline three-dimensional island growth was identified by in-situ reflection high-energy electron diffraction (RHEED) and ex-situ atomic force microscopy (AFM). X-ray diffraction (XRD) confirmed the presence of monoclinic HfO2 domains in crystallized films.
Authors: Shiro Hino, Tomohiro Hatayama, Naruhisa Miura, Tatsuo Ozeki, Eisuke Tokumitsu
Abstract: Low temperature deposition of HfO2 films on 4H-SiC(0001) substrates by pulse introduced metalorganic chemical vapor deposition (MOCVD) using tetrakis-diethylamido-hafnium [Hf[N(C2H5)2]4, (TDEAH)] and H2O has been investigated. HfO2 films with relatively low leakage current density of 10-4 A/cm2 were obtained even at a deposition temperature as low as 190 °C. We demonstrate that the HfO2/SiC interface, where the HfO2 was deposited at 190 °C, has lower interface state density than a typical thermally-grown SiO2/SiC interface. It is also shown by X-ray photoelectron spectroscopy (XPS) that the HfO2/SiC structure fabricated at 190 °C has lower SiOx count than the HfO2/SiC structure fabricated at 400 °C.
Authors: Jeong Hyun Moon, Da Il Eom, Sang Yong No, Ho Keun Song, Jeong Hyuk Yim, Hoon Joo Na, Jae Bin Lee, Hyeong Joon Kim
Abstract: The La2O3 and Al2O3/La2O3 layers were grown on 4H-SiC by atomic layer deposition (ALD) method. The electrical properties of La2O3 on 4H-SiC were examined using metal-insulator-semiconductor (MIS) structures of Pt/La2O3(18nm)/4H-SiC and Pt/Al2O3(10nm)/La2O3(5nm)/4H-SiC. For the Pt/La2O3(18nm)/4H-SiC structure, even though the leakage current density was slightly reduced after the rapid thermal annealing at 500 oC, accumulation capacitance was gradually increased with increasing bias voltage due to a high leakage current. On the other hand, since the leakage current in the accumulation regime was decreased for the Pt/Al2O3/La2O3/4H-SiC MIS structure owing to the capped Al2O3 layer, the capacitance was saturated. But the saturation capacitance was strongly dependent on frequency, indicating a leaky interfacial layer formed between the La2O3 and SiC during the fabrication process of Pt/Al2O3(10nm)/ La2O3(5nm)/ 4H-SiC structure.
Authors: M. Brezeanu, M. Badila, Gheorghe Brezeanu, F. Udrea, C. Boianceanu, G. Amaratunga, Konstantinos Zekentes
Abstract: A classical implementation of the field plate technique is the oxide ramp termination. This paper presents improvements of the breakdown voltage for both SiC JBDs and SBDs, obtained by using high-k dielectrics. A study regarding the influence of the dielectric permittivity and thickness on the off-state performances of the diodes is included. It is shown that Si3N4 is to be preferred to SiO2 for the dielectric ramp. Termination efficiencies up to 96% are reported.
Authors: W.J. Everson, V.D. Heydemann, Rick D. Gamble, David Snyder, G. Goda, Marek Skowronski, J.R. Grim, E. Berkman, Joan M. Redwing, J.D. Acord
Abstract: A new chemical mechanical polishing process (ACMP) has been developed by the Penn State University Electro-Optics Center for producing damage free surfaces on silicon carbide substrates. This process is applicable to the silicon face of semi-insulating, conductive, 4H, 6H, onaxis and off-axis substrates. The process has been optimized to eliminate polishing induced selectivity and to obtain material removal rates in excess of 150nm/hour. The wafer surfaces and resultant subsurface damage generated by the process were evaluated by white light interferometery, Transmission Electron Microscopy (TEM), Atomic Force Microscopy (AFM), and epitaxial layer growth. Residual surface damage induced by the polishing process that propagates into the epitaxial layer has been significantly reduced. Total dislocation densities measured on the ACMP processed wafers are on the order of the densities reported for the best as grown silicon carbide crystals [1]. Characterization of high electron mobility transistors (HEMTs) grown on these substrates indicates that the electrical performance of the substrates met or exceeded current requirements [2].

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