Silicon Carbide and Related Materials 2005

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Authors: J.L. Cantin, Hans Jürgen von Bardeleben
Abstract: Previous Electron Paramagnetic Resonance (EPR) studies identified the carbon dangling bond center as the main paramagnetic interface defect in 3C, 4H, 6H-SiC/SiO2. We demonstrate that this defect, called PbC center, can be passivated by forming gas annealing at 400°C. We have measured the PbC density at annealed 4H- and 3C-SiC/SiO2 interfaces and attributed its reduction to the transformation of the dangling bonds into EPR inactive C-H bonds. We have also studied the reverse phenomenon occurring during vacuum annealing at temperatures ranging from 600°C up to 1000°C and have determined a dissociation energy of ≈4.3 eV for the 3C and 4H polytypes.
Authors: Christoph Thill, Jan Knaup, Peter Deák, Thomas Frauenheim, Wolfgang J. Choyke
Abstract: The high density of interface electron traps in the SiC/SiO2 system, near the conduction band of 4H-SiC, is often ascribed to graphitic carbon islands at the interface, although such clusters could not be detected by high resolution microscopy. We have calculated the electronic structure of a model interface containing a small graphite-like precipitate of 19 carbon atoms, with a diameter of ~7 Å, corresponding to the experimental detection limit. The analysis of the density of states shows only occupied states in the band gap of 4H-SiC near the valence band edge, while carbon related unoccupied states appear only well above the conduction band edge.
Authors: S. Nie, R.M. Feenstra
Abstract: Scanning tunneling microscopy and spectroscopy have been used to study the electronic states of oxidized 6H-SiC interfaces. The SiC surfaces were oxidized by annealing in an ultra-high vacuum chamber at 600−800°C under 1×10-7 Torr pressure of molecular oxygen. Tunneling spectra revealed two dominant states at –1.8 and 1.5 eV relative to the Fermi level, which lie outside the band gap region but are inhomogeneously broadened such that they extend into the gap, together with additional features within the band gap.
Authors: Owen J. Guy, L. Chen, G. Pope, K.S. Teng, T. Maffeis, S.P. Wilks, Philip A. Mawby, T.E. Jenkins, A. Brieva, D.J. Hayton
Abstract: The investigation of the silicon carbide surface after a sacrificial silicon oxidation technique is reported. Oxidation of SiC is a necessary step in the fabrication of MOS devices and device termination features such as field plates. Device processing requires the etching of windows through the oxide layer to form features such as metal / SiC contacts. However, this work indicates that a thin interfacial Si-O-C layer is still present after etching the oxide with hydrofluric acid (HF). Ellipsometry and X-ray photoelectron spectroscopy (XPS) have been used to evaluate this interfacial layer formed after oxide growth and after subsequent removal of oxide layers. An XPS analysis of the surface after removal of the oxide revealed that silicon, oxygen and carbon were all present in the remaining layer, which could not be removed by annealing at temperatures up to 1000°C. The Si-O-C layer could be eliminated by altering the oxidation conditions or by using a sacrificial silicon layer oxidation process. Ni Schottky barrier diodes fabricated on the 4H-SiC surface after removal of the oxide, displayed slightly higher ideality factors than those of diodes fabricated on untreated 4H-SiC samples.
Authors: K. Kakubari, R. Kuboki, Yasuto Hijikata, Hiroyuki Yaguchi, Sadafumi Yoshida
Abstract: Real time observation of SiC oxidation was performed using an in-situ ellipsometer over the temperature range from 900°C to 1150°C. The relations between oxide thickness and oxidation time were obtained precisely by virtue of the real time measurements. We analyzed the relations between oxide thickness and oxidation time by applying the Deal and Grove model to obtain the linear and parabolic rate constants. Taking advantage of in-situ measurements, we successfully obtained the oxidation rate constants with high accuracy.
Authors: A.M. Hoff, E. Oborina
Abstract: Non-contact corona-voltage metrology is utilized to characterize as-grown thermal oxide films on 4H SiC substrates. Contact potential difference mapping is coupled with incremental application of corona charge to provide whole-wafer images of process related effects and multiplepoint capacitance-voltage characteristics respectively. Correspondence between wafer VCPD images and process details is suggested along with examples of fast electrical dielectric thickness determination and non-contact C-V characteristic acquisition.
Authors: Ruby N. Ghosh, Reza Loloee, Tamara Isaacs-Smith, John R. Williams
Abstract: SiC based field-effect devices are attractive for electronic and sensing applications above 250 °C. At these temperatures the reliability of the insulating dielectric in metal-oxidesemiconductor (MOS) structures becomes an important parameter in terms of long-term device performance. We report on the reliability of n-MOS SiC capacitors following thermal stress cycling in the 330 to 630 °C range. As the primary mode of oxide breakdown under these conditions is believed to be due to electron injection from the substrate, the gate leakage current was measured as a function of temperature. The gate dielectric was grown using dry oxidation with a post oxidation NO passivation anneal. For large area, 1 mm diameter, 6H-SiC capacitors we obtain current densities as low as 5nA/cm2 at 630 °C. In addition, gate leakage measurements from arrays of 300 to 1000 2m diameter devices fabricated on different 1cm2 6H-SiC substrates are presented. These are encouraging results for the long-term reliability of SiC field-effect sensors.
Authors: Kenji Fukuda, Makoto Kato, Shinsuke Harada, Kazutoshi Kojima
Abstract: SiC power MOSFETs are expected to be normally-off type fast switching devices. The on-resistance of SiC power MOSFETs is much higher than the value predicted from the physical properties of SiC. This is caused by the low channel mobility due to high interface state density (Dit). We have already reported that 4H-SiC MOSFETs on the C(0001 _ ) face had higher inversion-channel mobility. However, there is the SiO2/SiC interface roughness problem in SiC MOSFETs. There are many steps at the SiO2/SiC interface because a high off-angle is necessary for SiC epitaxial growth. These steps might make SiO2/SiC interfaces rough, which leads to reduction of channel mobility. In this work, we have investigated the effect of the SiO2/SiC interface roughness caused by the off-angle on the inversion channel mobility of 4H-SiC MOSFETs fabricated on the C(0001 _ ) face. The inversion-channel mobility of MOSFETs fabricated on the 4H-SiC C(0001 _ ) face substrate with the vicinal off-angle(0.8°) is higher than that of MOSFETs fabricated on the 4H-SiC C(0001 _ ) face substrate with the 8° off-angle. Reduction of the off-angle is very useful for improvement of channel mobility. A C(0001 _ ) epitaxial substrate with the vicinal off-angle would be suitable for SiC DMOSFETs.
Authors: Amador Pérez-Tomás, Phillippe Godignon, Jean Camassel, Narcis Mestres, Veronique Soulière
Abstract: 4H-SiC MOSFET devices with low temperature dry thermal oxidation (1050 °C 1 h) and TEOS plasma enhanced CVD deposited oxides on 4H-SiC substrates have been analysed in this paper. MOSFET transistors have been fabricated on the 4H-SiC (0001) Si face. The mobility improvement (up to 38-45 cm2/Vs) is remarkable compared with standard oxidation (<10 cm2/Vs). In addition, very high (but controversial) field-effect mobilities of around 216 cm2/Vs have also been extracted for MOSFETs fabricated on the (11-20) face. Taking into account the threshold voltage and the sub-threshold slope (S), we can see that we have three different ways to increase the mobility. First, by using (11-20) face material as already proposed. Second, by reducing the interface trap density as done with the low temperature thermal oxidation plus deposited oxide. And third, under the most favorable conditions with adequate TEOS deposition conditions. In this last case, the mobility improvement seems to be related with the gate current leakage more than (or together with) an interface traps reduction of the gate insulator.
Authors: Caroline Blanc, Dominique Tournier, Phillippe Godignon, D.J. Brink, Veronique Soulière, Jean Camassel
Abstract: We report on 4H-SiC MOSFET devices implemented on p-type <11-20>-oriented epitaxial layers, using a two-step procedure for gate oxide formation. First is a thin, dry, thermal SiO2 layer grown at 1050°C for 1 hour. Next, is a thick (50 nm) layer of complementary oxide deposited by PECVD using TEOS as gas precursor. With respect to the standard thermal oxidation process, this results in much improvement of the field effect mobility. For the best samples, we find a peak value in the range of 330 cm2/Vs while, on the full wafer, an average mobility of about 160 cm2/Vs is found. Up to now, this is one of the best results ever reported for 4H-SiC MOSFETs.

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