Materials Science Forum Vols. 527-529

Abstract: This paper is devoted to the results of a diffusion welding technique applied to solve the problem of packaging for large area SiC Schottky diodes. To supply low defect density substrates for fabrication of 0.3 cm2 Schottky diodes TDI defect-reducing technology was used. Diodes were fabricated on CVD grown low-doped 4H-SiC single epitaxial layer without edge termination. Double layer Ni-Au and triple layer Ti-Ni-Au sputter metallization were used for Schottky contacts fabrication. Non-rectifying backside contacts were provided by Ni-Au metallization. Diodes were tested on-wafer and delivered for dicing, and packaging. To decrease the parasitic spreading resistance the thickness of initial sputter metallization was increased by diffusion welded 30 μm metal foil. Combined thick and plane metal layers make it possible to perform the clamp mode package used in power electronics. This scheme of packaging ensures current takeoff from the whole contact area and allows operating temperatures up to 600°C. The forward current-voltage characteristics measured at 75 A measured for packaged diodes yields 250 A/cm2 (70A) at 1.9 V forward voltage. Reverse recovery time for packaged diodes was in the range of 29-36 ns.

Abstract: The Schottky barrier height (SBH) of Al, Ti, Au, and Ni contacts to n- and p-type 3C-SiC is investigated by means of I-V and C-V measurements. All metal contacts to n- (net donor concentration: 1.0 x 1016 /cm3) and p-type (net acceptor concentration: 4 x 1016 /cm3) 3C-SiC show the rectifying I-V characteristics except for Al contact to n-type 3C-SiC. Only Al contact to n-type 3C-SiC shows the ohmic characteristics. As the work function of metal is increased from 4.3 (Ti) to 5.2 (Ni) eV, SBH for n-type 3C-SiC is increased from 0.4 to 0.7 eV and SBH for p-type 3C-SiC is decreased from 2.2 to 1.8 eV. The small change of SBH for 3C-SiC may be correlated to the crystal orientation and the defects on the surface of 3C-SiC.

Abstract: We compared the electrical characteristics of 4H-SiC(0001) and (000-1) Schottky barrier diodes (SBDs), and derived the Schottky barrier heights (Hbs) of Ta, W, Mo, and Pd on {0001}. We investigated the annealing temperature dependence of Hbs in Mo and the W Schottky contacts for (0001) and (000-1). The Hbs are increased by annealing, except for the W Schottky contact on (0001). The yields of 0.25 cm2 as-deposited Mo-SBDs were 93.3% for (0001) and 71.1% for (000-1), respectively. We also demonstrated over 1 cm2 (0001) as-deposited Mo-SBD with a low leakage current, an excellent ideality factor, and no excess current, encouraging the enlargement of the active area in the SBD.

Abstract: 4H-SiC diodes with nickel silicide (Ni2Si) and molybdenum (Mo) Schottky contacts have been fabricated and characterised at temperature up to 400°C. Room temperature boron implantation has been used to form a single zone junction termination extension. Both Ni2Si and Mo diodes revealed unchanging ideality factors and barrier heights (1.45 and 1.3 eV, respectively) at temperatures up to 400°C. Soft recoverable breakdowns were observed both in Ni2Si and Mo Schottky diodes at voltages above 1450 V and 3400 V depending on the epitaxial structure used. These values are about 76% and 94% of the ideal avalanche breakdown voltages. The Ni2Si diodes revealed positive temperature coefficients of breakdown voltage at temperature up to 240°C.

Abstract: Silicon has been the semiconductor of choice for microelectronics largely because of the unique properties of its native oxide (SiO2) and the Si/SiO2 interface. For high-temperature and/or high-power applications, however, one needs a semiconductor with a wider energy gap and higher thermal conductivity. Silicon carbide has the right properties and the same native oxide as Si. However, in the late 1990’s it was found that the SiC/SiO2 interface had high interface trap densities, resulting in poor electron mobilities. Annealing in hydrogen, which is key to the quality of Si/SiO2 interfaces, proved ineffective. This paper presents a synthesis of theoretical and experimental work by the authors in the last six years and parallel work in the literature. High-quality SiC/SiO2 interfaces were achieved by annealing in NO gas and monatomic H. The key elements that lead to highquality Si/SiO2 interfaces and low-quality SiC/SiO2 interfaces are identified and the role of N and H treatments is described. More specifically, optimal Si and SiC surfaces for oxidation are identified and the atomic-scale processes of oxidation and resulting interface defects are described. In the case of SiC, we conclude that excess carbon at the SiC/SiO2 interface leads to a bonded Si-C-O interlayer with a mix of fourfold- and threefold-coordinated C and Si atoms. The threefold coordinated atoms are responsible for the high interface trap density and can be eliminated either by H-passivation or replacement by N. Residual Si-Si bonds, which are partially passivated by H and N remain the main limitation. Perspectives for the future for both Si- and SiC-based MOSFETs are discussed.

Abstract: Post-oxidation anneals that introduce nitrogen at the SiO2/4H-SiC interface have been most effective in reducing the large interface trap density near the 4H-SiC conduction band-edge for (0001) Si face 4H-SiC. Herein, we report the effect of nitridation on interfaces created on the (11 20) a-face and the (0001) C-face of 4H-SiC. Significant reductions in trap density (from >1013 cm-2 eV-1 to ~ 1012 cm-2 eV-1 at EC-E ~0.1 eV) were observed for these different interfaces, indicating the presence of substantial nitrogen susceptible defects for all crystal faces. Annealing nitridated interfaces in hydrogen results in a further reduction of trap density (from ~1012 cm-2 eV-1 to ~5 x 1011 cm-2 eV-1 at EC-E ~0.1 eV). Using sequential anneals in NO and H2, maximum field effect mobilities of ~55 cm-2 V-1s-1 and ~100 cm-2 V-1s-1 have been obtained for lateral MOSFETs fabricated on the (0001) and (11 20) faces, respectively. These electronic measurements have been correlated to the interface chemical composition.

Abstract: In this work, it was clarified that many dislocations present on the substrate surface markedly deteriorated the TDDB property of thermal gate oxide on commercially purchased 4H-SiC epitaxial substrates. However, it was also experimentally shown that even after removing all of the dislocations, there was still a significant difference in the charge-to-breakdown (QBD) value between thermal oxides on SiC and on Si. It was suggested that this difference might partly originate from the intrinsic physics. The ONO gate dielectric was shown to be a promising alternative to thermal oxide. Experimental results indicate that the ONO dielectric on 4H-SiC could achieve a higher QBD value than thermal oxide on Si. A value of QBD = 408 C/cm2 was achieved for an ONO gate dielectric, with a SiO2 equivalent thickness of 40 nm, on regular 4H-SiC.

Abstract: We report investigations of MOS and MOSFET devices using a gate oxide grown in the presence of sintered alumina. In contrast to conventionally grown dry or wet oxides these oxides contain orders of magnitude lower density of near-interface traps at the SiO2/SiC interface. The reduction of interface traps is correlated with enhanced oxidation rate. The absence of near-interface traps makes possible fabrication of Si face 4H-SiC MOSFETs with peak field effect mobility of about 150 cm2/Vs. A clear correlation is observed between the field effect mobility in n-channel MOSFETs and the density of interface states near the SiC conduction band edge in n-type MOS capacitors. Stable operation of such normally-off 4H-SiC MOSFET transistors is observed from room temperature up to 150°C with positive threshold voltage shift less than 1 V. A small decrease in current with temperature up to 150°C is related to a decrease in the field effect mobility due to phonon scattering. However, the gate oxides contain sodium, which originates from the sintered alumina, resulting in severe device instabilities during negative gate bias stressing.

Abstract: Two previously reported MOS processes, oxidation in the presence of metallic impurities and annealing in nitric oxide (NO), have both been optimized for compatibility with conventional 4H-SiC DMOSFET process technology. Metallic impurities are introduced by oxidizing in an alumina environment. This Metal Enhanced Oxidation (MEO) yields controlled oxide thickness (tOX) and robustness against high temperature processing and operation while maintaining high mobility (69 cm2/Vs) and near ideal NMOS C-V characteristics. Raising the NO anneal temperature from 1175oC to 1300oC results in a 67% increase in the mobility to 49 cm2/Vs with a slight stretch-out in the NMOS C-V. Both processes exhibit a small 30% mobility reduction in MOSFETs fabricated on NA = 1x1018 cm-3 implanted p-wells. The low field mobility in the MEO MOSFETs is observed to increase dramatically with measurement temperature to 160 cm2/Vs at 150oC.