Materials Science Forum Vols. 527-529

Abstract: The impurity concentration dependence of the recrystallization rate of phosphorus implanted 4H-SiC(11-20) has been investigated by means of Rutherford backscattering spectrometry in the annealing temperature range from 660 to 720 oC . The phosphorus ions were multiply implanted to form the implantation layer with the thickness of 200 nm and the phosphorus concentration of 1 x 1020, 4 x 1020, or 1 x 1021 /cm3, respectively. The recrystallization rate of the P ion implantation-induced amorphous layer in 4H-SiC(11-20) increases with an activation energy of 3.4 eV as does the case of the Ar ion implantation-induced amorphous layer in 6H-SiC(11-20) and (1-100). As the P concentration is increased from 1 x 1020 to 1 x 1021 /cm3, the recrystallization rate is enhanced from 3.5 to about 5nm/min, while the recrystallization rate for the Ar implantationinduced amorphous layer was 1.5 nm/min. It is suggested that the recrystallization process is enhanced by the presence of the substitutional impurity at the amorphous-crystalline interface during the recrystallization.

Abstract: We perform rapid thermal annealing (RTA) on areas as large as 2-inch φ (diameter) at high temperature using the hybrid super RTA (HS-RTA) equipment. The HS-RTA equipment consists of an infrared annealing unit and a RF induction annealing unit in order to uniformly anneal over 2-inch φ susceptor. As a result of annealing by the HS-RTA equipment, the temperature is elevated from RT to peak temperature (~1800°C) for less than 1 min, remain stable at annealing temperature for 30s and falls from peak temperature to 1000°C within less than 20s. The temperature distributions on a 2-inch φ susceptor are ±10°C, ±33°C and ±55°C at 1565°C, 1671°C and 1752°C, respectively. Phosphorus (P) ion implanted silicon carbide (SiC) samples are used to evaluate the performance of the HS-RTA equipment. The five implanted samples placed on the 2-inch φ susceptor are annealed for 30s at 1565°C, 1671°C and 1752°C. The mean sheet resistances of the 5 samples annealed at 1565°C, 1671°C and 1752°C are 92.6Ω/􀀀, 82.6Ω/􀀀 and 75.5Ω/􀀀, respectively. The sheet resistance uniformities are 9.9%, 7.9% and 9.3%. The average roughness (Ra) is calculated from 10 μm square Atomic Force Microscopy (AFM) image. Ra values of the samples annealed at 1565°C, 1671°C and 1752°C are 2.399 nm, 2.408 nm and 3.282 nm, respectively.

Abstract: We developed EBAS-100, which is available to 100 mm diameter SiC wafer, for post ion implantation annealing in order to realize silicon carbide (SiC) device with large volume production. EBAS-100 is able to perform the rapid thermal process due to the vacuum thermal insulation and small heat capacity of susceptor. Electrical power consumption density was 18.8 Wh/cm2 for EBAS-100, which is one-third smaller than that of our previous system (EBAS-50). Samples used in this study were p-type epitaxial 4H-SiC (0001) grown on 8o off SiC substrate. P+ ions (total dose; 2.0 x 1016 /cm2, thickness; 350 nm) were implanted into SiC samples at 500 oC. The root-mean-square (RMS) of surface roughness is estimated to be 0.21 nm for the sample annealed at 1700 oC for 5 min, which is much smooth than that of the sample annealed by the conventional RF inductive annealing (RMS value: 5.97 nm). Averaged sheet resistance (RS) value of 63.3 ohm/sq. is obtained with the excellent non-uniformity of RS (+/- 1.4 %) for the diameter of 76.0 mm.

Abstract: This paper reports on the defects created in a 6H-SiC p-type substrate by a process of ion implantation and a quite low temperature annealing (1300 °C), suitable for the realization of the source/drain regions of a MOSFET because it does not give rise to step bunching phenomena. Current voltage measurements showed the presence of a group of diodes featured by excess current. The effects of defects under the implanted layer on the transport properties of the diodes were investigated by DLTS: four hole traps were detected in all the measured diodes; besides, a broadened peak around 550 K was detected in the diodes that show excess current.

Abstract: An n-type 8° off-axis <0001> 4H-SiC epitaxial wafer was processed. The n-type epilayer had doping and thickness of, respectively, ~3 × 1015 cm-3 and ~5 μm. p+/n diodes with not terminated junctions were constructed by a selective area implantation process of 9.2 × 1014 cm-2 Al+ ions at 400°C. The diodes had areas in the range 2×10-4 -1×10-3 cm2. The Al depth profile was 6×1019 cm-3 high and 164 nm thick. The post implantation annealing process was done in a high purity Ar ambient at 1600°C for 30 min. The diode current-voltage characteristics were measured in the temperature range 25-290°C. Statistics of 50-100 measurements per device type were done. The fraction of diodes that could be modeled as abrupt junctions within the frame of the Shockley theory decreased with increasing area value, but was always > 75%. The ideality factor was > 2 only at temperatures > 200°C and bias values < 1 V. The leakage current was extremely weak and remained of the order of 10-9 Acm-2 at 70°C and 500 V reverse bias. 4% of the diodes reached the theoretical voltage breakdown that was 1030 V. The surface roughness of un-implanted and implanted regions after diode processing was, respectively, 2 nm and 12 nm.

Abstract: This work reports the realization and characterization of 4H-SiC p+/n diodes with the p+ anodes made by Al+ ion implantation at 400°C and post-implantation annealing in silane ambient in a cold-wall low-pressure CVD reactor. The Al depth profile was almost box shaped with a height of 6×1019 cm-3 and a depth of 160 nm. Implant anneals were performed in the temperature range from 1600°C to 1700°C. As the annealing temperature was increased, the silane flow rate was also increased. This annealing process yields a smooth surface with a roughness of the implanted area of 1.7 - 5.3 nm with increasing annealing temperature. The resistivity of the implanted layer, measured at room temperature, decreased for increasing annealing temperatures with a minimum value of 1.4 0-cm measured for the sample annealed at 1700°C. Considering only the current-voltage characteristic of a diode that could be modeled as an abrupt p/n junction within the frame of the Shockley theory, the diode process yield and the diode leakage current decreased, respectively, from 93% to 47% and from 2×10-7 Acm-2 to 1×10-8 Acm-2 at 100 V reverse bias, for increasing post implantation annealing temperature.

Abstract: Characterization of post implantation annealing steps is done by extracting the activation and compensation data of implanted Al atoms. Usually, this is done by Hall measurements. The preparation of Hall samples and temperature dependent Hall measurements, however, are rather complex compared to, e.g., temperature dependent resistivity measurements by 4-point probing. Therefore, a model for extracting relevant electrical parameters from resistivity data has been developed. The model is based on the neutrality equation and a temperature dependent mobility model.

Abstract: SiC samples implanted at 600°C with 1018, 1019, or 1020 cm-3 of Al to a depth of ~ 0.3 μm and annealed with a (BN)AlN cap at temperatures ranging from 1300 – 1700°C were studied. Some of the samples have been co-implanted with C or Si. They are examined using Hall, sheet resistivity, CL, EPR, RBS, and TEM measurements. In all instances the sheet resistance is larger than a comparably doped epitaxial layer, with the difference being larger for samples doped to higher levels. The results suggest that not all of the damage can be annealed out, as stable defects appear to form, and a greater number or more complex defects form at the higher concentrations. Further, the defects affect the properties of the Al as no EPR peak is detected for implanted Al, and the implanted Al reduces the AlSi peak intensity in bulk SiC. CL measurements show that there is a peak near 2.9941 eV that disappears only at the highest annealing temperature suggesting it is associated with a complex defect. The DI peaks persist at all annealing temperatures, and are possibly associated with a Si terminated partial dislocation. TEM analyses indicate that the defects are stacking faults and/or dislocations, and that these faulted regions can grow during annealing. This is confirmed by RBS measurements.

Abstract: We investigate the effect of surface orientation and off-angle for Al-implanted 4H-SiC samples after high temperature annealing. The samples are obtained from a 4H-SiC (0001) substrate 8° off-angled (Si-face 8°off), and (000-1) substrates 8° (C-face 8°off), 4° (C-face 4°off) and less than 1° off-angled (C-face ~1°off). An n-type epitaxial layer is deposited on all substrates. Multiple implantations of Al+ (30~200keV) are carried out at 600°C. The total dose is 8.6 × 1015 cm-2. The Al-implanted samples are annealed in Ar ambient at 1580°C, 1700°C and 1800°C for 30s using the hybrid super rapid thermal annealing (HS-RTA) equipment. In this study, sheet resistance (Rs), free carrier concentration (Ns), Hall mobility (μ) and root-mean square roughness (Rrms) are used to evaluate the Al-implanted samples after high temperature annealing. Rs for all Al-implanted samples after annealing at 1800°C for 30s is around 18k/. Rrms for the Al-implanted C-face samples after annealing at 1800°C increases with increasing off-angle. Rrms for the Al-implanted Si-face 8°off sample after annealing increases with annealing temperature. Rrms for the C-face ~1°off Al-implanted sample after annealing at 1800°C is lower than that for the Si-face 8°off Al-implanted sample after annealing at 1700°C, moreover Rs for the C-face ~1°off sample after annealing at 1800°C is about 10% of that for the Si-face 8°off Al-implanted sample after annealing at 1700°C. It is shown that the C-face ~1°off sample is useful to fabricate a p+ region with low Rs and low Rrms. If C-face 4H-SiC is used to fabricate devices, devices made on C-face 4H-SiC with low off angle are expected to decrease any problems caused by increase of surface roughness after high temperature annealing (~1800°C).