Silicon Carbide and Related Materials 2005

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Authors: Sima Dimitrijev, Ji Sheng Han, Jin Zou
Abstract: High-resolution transmission electron microscopy (HR TEM) reveals an atomically flat SiC surface after oxidation in either NO or dry O2 ambients. This reopens the question of the origin of the electronically active defects at the SiO2–SiC interface, whose density remains orders of magnitude higher than in the SiO2–Si interface. Capacitance-transient measurements, analysed in this paper, demonstrate that the dominant electronically active defects are in the oxide at tunneling distances from the SiC surface (near-interface traps). The HR TEM results cannot rule out that these traps are related to carbon/oxygen bonds or even nanometer-sized carbon clusters, which resolves the apparent inconsistency with the earlier experimental evidence of carbon accumulation at (or near) the SiO2–SiC interface.
975
Authors: Antonella Poggi, Francesco Moscatelli, Andrea Scorzoni, Giovanni Marino, Roberta Nipoti, Michele Sanmartin
Abstract: Many investigations have been conducted on the growth conditions of SiO2 on SiC to improve the oxide quality and the properties of the silicon carbide-silicon dioxide interface. In this work a comparison between a wet oxidation and an oxidation in N2O ambient diluted in N2 is proposed. The interface state density Dit near the conduction-band edge of SiC has been evaluated by conventional C-V measurements obtaining results similar or better than the literature data. Furthermore, the slow trapping phenomena have been studied and preliminary results are reported.
979
Authors: Kevin Matocha, Chris S. Cowen, Richard Beaupre, Jesse B. Tucker
Abstract: 4H-SiC MOS capacitors were used to characterize the effect of reactive-ion etching of the SiC surface on the electrical properties of N2O-grown thermal oxides. The oxide breakdown field reduces from 9.5 MV/cm with wet etching to saturate at 9.0 MV/cm with 30% reactive-ion over-etching. Additionally, the conduction-band offset barrier height, φB, progressively decreases from 2.51 eV with wet etching to 2.46 eV with 45% reactive-ion over-etching.
983
Authors: Tsunenobu Kimoto, H. Kawano, Masato Noborio, Jun Suda, Hiroyuki Matsunami
Abstract: Oxide deposition followed by high-temperature annealing in N2O has been investigated to improve the quality of 4H-SiC MOS structures. Annealing of deposited oxides in N2O at 1300oC significantly enhances the breakdown strength and decreases the interface state density to 3x1011 cm-2eV-1 at EC – 0.2 eV. As a result, high channel mobility of 34 cm2/Vs and 52 cm2/Vs has been attained for inversion-type MOSFETs fabricated on 4H-SiC(0001)Si and (000-1)C faces, respectively. The channel mobility shows a maximum when the increase of oxide thickness during N2O annealing is approximately 5 nm. A lateral RESURF MOSFET with gate oxides formed by the proposed process has blocked 1450 V and showed a low on-resistance of 75 mcm2, which is one of the best performances among lateral SiC MOSFETs reported.
987
Authors: Florin Ciobanu, Thomas Frank, Gerhard Pensl, Valeri V. Afanas'ev, Sheron Shamuilia, Adolf Schöner, Tsunenobu Kimoto
Abstract: A near-surface Gaussian nitrogen (N) profile is implanted into the Si- or C-face of n-/ptype 4H-SiC epilayers prior to a standard oxidation process. The corresponding MOS capacitors are investigated by conductance and internal photoemission spectroscopy. The effect of N-implantation on the density of interface traps Dit is studied and a model is proposed, which consistently explains the observed results.
991
Authors: Bharat Krishnan, Hrishikesh Das, Yaroslav Koshka, Igor Sankin, P.A. Martin, Michael S. Mazzola
Abstract: Dielectric charges and charge stability were compared in different dielectrics formed on SiC by different processing techniques. The concentration and transient behavior of the interface and trapped charges were investigated. Strong hysteresis and flat-band voltage drift under applied bias were observed in some of the samples. They are attributed to the trapping of the charge injected in the dielectrics. Differences in charge injection, charge trapping, and capture/emission of carriers by interface traps were pronounced for the investigated SiO2 and Si3N4 dielectrics.
995
Authors: Junji Senzaki, Atsushi Shimozato, Kenji Fukuda
Abstract: Low-temperature post-oxidation annealing (POA) process of high-reliability thermal oxides grown on 4H-SiC using new apparatus that generates atomic hydrogen radicals by high-temperature catalyzer has been investigated. Atomic hydrogen radicals were generated by thermal decomposition of H2 gas at the catalyzer surface heated at high temperature of 1800°C, and then exposed to the sample at 500°C in reactor pressure of 20 Pa. The mode and maximum values of field-to-breakdown are 11.0 and 11.2 MV/cm, respectively, for the atomic hydrogen radical exposed sample. In addition, the charge-to-breakdown at 63% cumulative failure of the thermal oxides for atomic hydrogen radical exposed sample was 0.51 C/cm2, which was higher than that annealed at 800°C in hydrogen atmosphere (0.39 C/cm2). Consequently, the atomic hydrogen radical exposure at 500°C has remarkably improved the reliability of thermal oxides on 4H-SiC wafer, and is the same effect with high-temperature hydrogen POA at 800°C.
999
Authors: Yasuto Hijikata, Hiroyuki Yaguchi, Sadafumi Yoshida, Y. Takata, K. Kobayashi, H. Nohira, T. Hattori
1003
Authors: Daniel B. Habersat, Aivars J. Lelis, G. Lopez, J.M. McGarrity, F. Barry McLean
Abstract: We have investigated the distribution of oxide traps and interface traps in 4H Silicon Carbide MOS devices. The density of interface traps, Dit, was characterized using standard C-V techniques on capacitors and charge pumping on MOSFETs. The number of oxide traps, NOT, was then calculated by measuring the flatband voltage VFB in p-type MOS capacitors. The amount that the measured flatband voltage shifts from ideal, minus the contributions due to the number of filled interface traps Nit, gives an estimate for the number of oxide charges present. We found Dit to be in the low 1011cm−2eV−1 range in midgap and approaching 1012 −1013cm−2eV−1 near the band edges. This corresponds to an Nit of roughly 2.5 ⋅1011cm−2 for a typical capacitor in flatband at room temperature. This data combined with measurements of VFB indicates the presence of roughly 1.3 ⋅1012cm−2 positive NOT charges in the oxide near the interface for our samples.
1007
Authors: Morgan S. Dautrich, Patrick M. Lenahan, Aivars J. Lelis
Abstract: In this study we report on spin-dependent recombination-detected electron spin resonance of interface/near interface defects in 4H-SiC metal oxide semiconductor field effect transistors with thermally grown SiO2 gate stacks. We demonstrate a distribution of performance-limiting defects which extends beyond the SiC/SiO2 boundary into the SiC bulk. Our results strongly indicate that the defects are intrinsic and we tentatively identify them as silicon vacancy-like centers on the basis of strong, but imprecisely-resolved, 29Si hyperfine sidepeaks in the magnetic resonance spectrum.
1011

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