Abstract: Threshold voltage models for both buried channel and surface channel for the dual-channel strained Si/strained Si1-xGex/relaxd Si1-yGey(s-Si/s-SiGe/Si1-yGey) p-type metal-oxide-semiconductor field-effect transistor (PMOSFET) are presented in this paper. And the maximum allowed thickness of s-Si is given, which can ensure that the strong inversion appears earlier in the buried channel (compressive strained SiGe) than in the surface channel, because the hole mobility in the buried channel is higher than that the surface channel. They offer a good accuracy as compared with the results of device simulator ISE.
Abstract: An analytical expression for collector resistance of a novel vertical SiGe partially-depleted accumulation-subcollector HBT on thin SOI is obtained. Supported by simulation result, the resistance decreases quickly with the increase of substrate-collector bias and improves the transit frequency dramatically. The model is found to be significant in the design and simulation of 0.13 μm millimeter wave SiGe SOI BiCMOS technology.
Abstract: The impact of Drain-Induced Barrier Lowering effect (DIBL) on the shift of threshold voltage is prominent as the feature size of MOS device continue reducing. In this paper, a threshold voltage model for small-scaled strained Si nMOSFET is proposed to illustrate the impact of DIBL effect on the threshold voltage, which is based on the distribution of the charge in depletion layer when strong inversion occurred. By simulation, the influence of DIBL to variation threshold voltage with its design physical and geometric parameters can be predicted, such as gate length, drain bias, Ge content, oxide thickness, source/drain junction depth, and doping concentration. This model is significant for the design of high performance strained Si nMOSFET to restrain the DIBL effect.
Abstract: In this paper, a method of determining physical dimension of Double Barrier Quantum Well (DBQW) of Resonance Tunneling Diodes (RTDs) is presented by using I-V characteristic governing on them. In this procedure, first we have used performance metrics related to RTDs I-V characteristic such as Peak to Valley Current Ratio (PVCR), peak current density (JP), valley current density (JV) and Voltage Swing (VS), and by some other arbitrary points, we have fitted a curve to the RTD current-voltage equation by MATLAB software. Then we have obtained the physical parameter of I-V equation and adjusted some of them with modification coefficients. Next, by choosing the material of barriers and the well and amount of doping, we have calculated the thicknesses of both. To review the mentioned method, the experimental result of I-V characteristic of the sample structure DBQW is considered and we have come to this idea that the dimensions gained out of this method are highly correlated with those of the experimental sample.
Abstract: Use MBE technology grew three different structures’ RTD to get a contrast test on device with different thickness of well structure’s DC character,they all grew on semi-insulating GaAs substrates, and use I-V analysis instrument tested the I-V character of the RTD in room temperature, in the test results , the PVCR of the best device was up to 7.1,VP is reduced to 0.4V ,then we analyzed the relationship between the device material structure and I-V character , this paper provided a reference for the better performance of the RTD structure design.
Abstract: In order to obtain the aerial target’s electrostatic information, a novel electrostatic detection sensor is proposed. With the help of simulating method, the characteristics curve which contains the target’s position and orientation is acquired. Then the electrostatic detection sensor is tested with the help of experiment, results indicate performance of the electrostatic detection sensor is related to target’s some parameters, sensor’s layout and sensitivity of relevant circuit. It provides the basis for further practicality.
Abstract: (Pb0.92La0.08)(Zr0.65Ti0.35) O3(PLZT) thin films were fabricated on indium-doped tin oxide (ITO)-coated glass substrates to create transparent capacitor by the sol-gel method following annealing process. X-ray diffraction analysis shows that the PLZT thin films are polycrystalline with a single perovskite phase at 650°C. The ferroelectric, electrical and optical properties of these films were investigated in detail as a function of annealing temperature. Measurements with the PLZT films annealed at 650°C yielded the following: relative permittivity≈775 and dielectric loss (tanδ) ≈0.054, leakage current of 7.1× 10-9A, and remanent polarization of 38 μC/cm2 and the coercive electric field of 55 kV/cm and transparency of 88%. The pure perovskite films exhibit better properties than those films which have some fraction of pyrochlore phase.
Abstract: Carbon encapsulated nickel nanoparticles (CENNPs) with high purity were fabricated by laser ablation of nickel target in ethanol. The size of CENNPs varies from tens to hundreds of nanometers, and CENNPs show two kinds of typical morphologies i. e. a nickel core with a carbon shell or a nickel core with two carbon shells. Transmission electron microscopy indicated that the CENNPs formed as a result of laser evaporation of the nickel target and the decomposition of ethanol, whose carbon atoms mixed with the nickel vapor, and Ni/C liquid droplets appeared during the cooling stage. The carbon shells formed by precipitation of carbon atoms on the surface of the nickel cores led to the formation of CENNPs.
Abstract: The electronic transport properties of an (8, 0) SiC nanotube (SiCNT) with antisite defect are investigated with the method combined non-equilibrium Green’s function with density functional theory, in which the defect is formed with a carbon atom being substituted by a silicon atom. In transmission spectrum of the nanotube, a transmission valley about 1.68 eV near the Fermi energy is discovered, which indicates that the nanotube is a wide band-gap semiconductor. In its current-voltage characteristic, turn-on voltages of ±1.0 V are found under positive and negative bias. This originates from more orbital participating in its electronic transport properties caused by the bias. These results are meaningful to investigations on working mechanisms of SiCNT electronic devices.
Abstract: This paper proposes a high efficiency power amplifier with a diode linearizer and voltage combining transformers in a standard 0.13-μm TSMC CMOS technology. The 3-D simulated transformer adopts multi-finger architecture which provides low insertion loss and allows high current capacity on the transformer. With the 4 differentially cascaded connected multi-finger transformers, the amplifier delivers more than 1W output power under 1.8 V supply condition. To enhance linearity of the power amplifier, the diode configuration bias circuit is used in this paper. With all integration of transformers, balun, diode bias circuits and same 4 diff-amps, the prototype Class AB Power Amplifier shows 32dBm saturation power at 2.4 GHz. Due to the diode linearizer the output P1dB is 30.8 dBm with 28 % Power Added Efficiency.