Abstract: The behavior of 200nm Cr Schottky contacts on n-type 4H-SiC has been investigated with photoelectron spectroscopy (XPS) and standard (I-V and C-V) electrical measurements at different measurement temperatures. A barrier height close to 1.2 eV was calculated from XPS data under no-current and no-bias conditions on ultra-thin Cr films grown in-situ under UHV conditions. The I-V measurements on as-deposited contacts resulted in a barrier height of 1.06 eV while a value of 1.2 eV has been extracted from the C-V measurements.
Abstract: Previous simulation works and experiments on the loss of 4H-SiC floating junction Schottky barrier diodes (Super-SBDs) show that the loss is related to the doping concentration in the drift region and the pattern of the floating layer. The effect of the doping concentration for lowering the loss is characterized the breakdown voltage (Vbd) and the on-state resistances (RonS) of the Super-SBDs based on Baliga’s figure of Merit (BFOM). Experimental devices with two doping concentrations in the drift region are fabricated to investigate the static characteristics: Vbd and RonS. The Vbd of the Super-SBDs is close to the simulation result, near 3000 V. However the tendency of the Vbd by the doping concentration is not similar to the simulation result. And the RonS are about 3.22 mcm2 which is higher than that of simulation result. The doping concentration optimized in this study does not show significant lowering loss and the design of the floating layer in the termination region affect the low-loss static characteristics of the Super-SBD. In addition, adopting PiN structure with floating layer (Super-PiN) affects the low-loss dynamic characteristics, optimizing the doping concentration in the drift region. We conclude that the fabricated Super-SBDs with the floating layer in the termination region, the drift region with a doping concentration of 1.01016 cm-3 and mesa-shaped termination structure, have excellent Vbd of 2990 V which is almost same as that of simulation result and RonS of 3.22 mcm2.
Abstract: SiC Diodes in the 300 to 1200V range have steadily increased their market penetration in the last 7 years. Especially the 600V SiC diodes are a nearly mandatory device for further increase of power density in modern switch mode power supplies. Those devices entered the market from the high end side due to the still significant higher costs in comparison with conventional fast Si diodes. On the other hand, these high end markets like server or telecom power supplies also require very high reliability of the devices used. In previous papers we showed, that Merged-PN-Schottky (MPS) diodes can be designed for avalanche ruggedness [1,2].
In this paper we will describe, how this feature supports overall reliability improvement. Addditionally, we will show, how a conventional SiC Schottky diode without MPS structure can be modified in order to achieve stable avalanche breakdown in combination with strong reliability improvement.
Abstract: The effects of post annealing etch process on electrical performances of a 4H-SiC Schottky diodes without any edge termination were investigated. The post etch was carried out using various dry the dry etch techniques such as Inductively Coupled Plasma (ICP) and Neutral Beam Etch (NBE) in order to eliminate suspicious surface damages occurring during a high temperature ion activation process. The leakage current of diodes treated by NBE measured at -100V was about one order lower than that of diode without post etch and a half times lower than that of diode treated by ICP without a significant degradation of forward electrical characteristics. Based on the above results, the post annealing process was adapted to a junction barrier Schottky diode with a field limiting ring. The blocking voltages of diode without post annealing etch and diodes treated by ICP and NBE were -1038V, -1125V, and -1595V, respectively.
Abstract: The impact of barrier tunneling on SiC-JBS performance is studied both experimentally and theoretically. We show that although the pinch-off effects associated with the JBS structure can significantly suppress the surface electric field, barrier tunneling still dominates the reverse behavior. Barrier tunneling determines the apparent breakdown voltage, as well as the apparent breakdown voltage vs. forward voltage drop trade-off of the JBS diode in practical applications.
Abstract: Schottky barrier diodes and junction barrier Schottky diodes are investigated by thermal admittance spectroscopy, and by Capacitance-Voltage measurements. Samples are protected with surrounding junction termination extension and p+ ring. Temperature dependence of the doping level is first calculated. Then admittance spectra allow detecting defects and extracting their activation energies and capture cross sections. Results seem to indicate the presence of interfacial defects and defects due to the implantation process.
Abstract: The avalanche breakdown characteristics of a graded p+-n junction formed with aluminum ion-implantation for 4H-SiC were investigated. The breakdown voltage of the graded p+-n junction was calculated using a commercial process/device simulator and considering the ion-implanted distribution of aluminum. To compare the calculated results to the experimental results, a p+/n/n+ diode with an aluminum ion-implanted p+-layer was fabricated on a 2.8-μm-thick 1.1 × 1017-cm-3 n-type epitaxial layer. The breakdown voltage of the fabricated diode showed a higher breakdown voltage than that of the calculation. The cause of the difference in the breakdown voltages between the fabricated diode and the calculation is discussed.
Abstract: Electrical properties of p+n 4H-SiC(0001) diode formed by Al ion implantation to n-type epitaxial layer have been investigated as a function of Al doping concentration ranging from 1 x 1020 to 6 x 1020 /cm3 and the operation temperature. The n-type 4H-SiC(0001) epitaxial layer with a net donor concentration of 1 x 1016 /cm3 are multiply implanted by Al ions in the energy range from 30 to 170 keV at elevated temperature of 500 oC with a implantation layer thickness of 350 nm, followed by the annealing at 1900 oC for 1min using EBAS. On-state resistance of diode with Al concentration of 1 x 1020 /cm3 is estimated to be about 4.5 mcm2, while that for diode with Al concentration of 6 x 1020 /cm3 is 1.8 mcm2 at 25 oC. In the sample with Al concentration of 6 x 1020 /cm3 shows the positive temperature coefficient of on-state resistance of diode, while that for sample with Al concentration less than 3 x 1020 /cm3 is negative. The diode formed by Al implantation at the concentration of 6 x 1020 /cm3 is able to operate at the constant current density of 80 A/cm2 at the bias of 2.9 V independent to operation temperature.
Abstract: We have fabricated the four pn-type junction TEGs (Test Element Groups) having different structure. Those TEGs are close to the double-implanted (Di) MOSFETs, step by step from the simple pn diode. Voltage-current (V-I) characteristics of the hundred TEGs having p-well structure show similar blocking characteristics of those of simple pn diodes on the same wafer. This indicates that the p-well structure itself does not cause a significant deterioration on the blocking yield. On the other hand, the yield is significantly influenced by the annealing condition for ion-implanted layer. The oxide-related hard breakdown on the JFET region dominates the blocking yield. The reach-through breakdown of the TEGs having the n+ region within each p-well becomes largely suppressed by the high-temperature and short-time annealing.
Abstract: Phosphorous implanted n+/p diodes have been included in the masks for manufacturing n-MOSFET devices and processed in the same way of source/drain regions. The diode junctions were made by a P+ implantation at 300°C and a post implantation annealing at 1300°C. The diode emitter area was protected by 0.6 m thick CVD oxide during the processing of the MOSFET gate oxide. Three gate oxide processes were taken into account: two of them include a N implantation before a wet oxidation, while the third one was a standard oxidation. Considering the effect on the n+/p diodes, the main difference among the processes were the wet thermal oxidation time that ranged between 180 and 480 min at a temperature of 1100°C. The diode current-voltage characteristics show similar forward but different reverse curves in the temperature range of 25-290°C. Differences in reverse bias voltage as a function of the measurement temperature have been analyzed and are related to the different gate oxidation time. A correlation between the shortest oxidation time and the lower leakage current is presented.