Materials Science Forum Vols. 615-617

Abstract: In silicon carbide devices used above around 2.4 kV, effective anode edge termination usually requires a high-resolution floating guard ring implant or multiple lithography/implant cycles to effect a multi-zone junction termination extension. In general the goal is to produce a smoothly tapered field profile to prevent high-voltage field-crowding that causes premature breakdown at the edge of the high voltage electrode. Using a much simpler grayscale photolithographic technique and a single termination implant, we directly produce the desired tapered doping profile. The effectiveness of this termination is shown by the near-ideal (6.1 kV) breakdown measured in PiN diodes made with a 38 µm intrinsic layer. The simple method is applicable to the fabrication of many high-voltage devices.

Abstract: A polyimide (PI) has been used for the passivation of maximum 7.8 kV 4H-SiC P+N–N+ (PiN) diodes with a 60 µm-thick base epilayer and a junction termination extension (JTE) periphery protection. The dielectric strength of PI films is studied versus area and temperature. The reverse electrical characterization of the PI–passivated PiN diodes is presented for different natures of the environmental atmosphere. The results are compared to those obtained from same devices passivated with a deposited SiO2 thick film. The highest experimental breakdown voltages are obtained for PI–passivated PiN diodes immersed in PFPE oil, with a 5-6 kV typical value, and a 7.3 kV maximum value. Experimental observations are discussed in correlation with the insulating film properties.

Abstract: Lifetime measurements are performed on 4H-SiC pin power diodes (6.5 kV). The lifetime values in the base range from 1.1 s to 2.1 s; these values demonstrate the high quality of the 4H-SiC epilayer and the optimized device processing. The observed lifetimes are correlated with deep defect centers detected by deep level transient spectroscopy. The role of the Z1/2-center as a lifetime killer is discussed.

Abstract: This paper reports on the influence of temperature on the electrical carrier lifetime of a 3.3 kV 4H-SiC PiN diode processed with a new generation of SiC material. The Open Circuit Voltage Decay (OCVD) is used to evaluate ambipolar lifetime evolution versus temperature. The paper presents a description of the setup, electrical measurements and extraction fittings. The ambipolar lifetime is found to rise from 600 ns at 30 °C to 3.5 μs at 150 °C.

Abstract: The breakdown failure points in the 4H-SiC PiN diodes were analyzed by the electron beam induced current (EBIC). We focused on the failure, which showed the avalanche breakdown, and we determined the failure points by an emission microscopy. We observed the basal plane dislocation around the failure point and at measured temperatures below 200K we found the dark spots in the EBIC. However, in the X-ray topography image, no spots were found around the dislocations. We therefore think that these spots originated from the metal contamination. The electric field was multiplied due to a permittivity change, and this multiplication caused the avalanche breakdown.

Abstract: High-voltage vertical-junction-field-effect-transistors (VJFETs) are typically designed normally-on to ensure low-resistance voltage-control operation at high current-gain. To exploit the high-voltage/temperature capabilities of VJFETs in a normally-off voltage-controlled switch, high-voltage normally-on and low-voltage normally-off VJFETs were connected in the cascode configuration. The cascode gate’s threshold voltage decreases from 2.5 V to 2 V as the temperature increases from 25°C to 225°C, while its breakdown voltage increases from -23 V to -19 V. At 300°C, the drain current of the cascode switch is 21.4% of its 25°C value, which agrees well with the reduction of the 4H-SiC electron mobility with temperature. The VJFET based all-SiC cascode switch is normally-off at 300°C, with its threshold voltage shifting from 1.6 V to 0.9 V as the temperature increases from 25°C to 300°C. This agrees well with the measured reduction in VJFET built-in potential. Finally, the reduction in cascode transconductance with temperature follows that of the theoretical 4H-SiC electron mobility. Overall, the measured thermally-induced cascode parameter shifts are in excellent agreement with theory, which signifies fabrication of robust SiC VJFETs for power switching applications.

Abstract: Prototype 800 V, 47 A enhancement-mode SiC VJFETs have been developed for high temperature operation (250 °C). With an active area of 23 mm2 and target threshold voltage of +1.25 V, these devices exhibited a 28 m room temperature on-resistance and excellent blocking characteristics at elevated temperature. With improved device packaging, on-resistance and saturation current values of 15 m and 100 A, respectively, are achievable.

Abstract: Electron-hole recombination-induced stacking faults have been shown to degrade the I-V characteristics of SiC power p-n diodes and DMOSFETs with thick drift epitaxial layers. In this paper, we investigate the effect of bipolar gate-to-drain current on vertical-channel JFETs. The devices have n- drift epitaxial layers of 12-μm and 100-μm thicknesses, and were stressed at a fixed gate-to-drain current density of 100 A/cm2 for 500 hrs and 5 hrs, respectively. Significant gate-to-drain and on-state conduction current degradations were observed after stressing the 100-μm drift VJFET. Annealing at 350°C reverses the stress induced degradations. After 500 hours of stressing, the gate-to-source, gate-to-drain, and blocking voltage characteristics of the 12-μm VJFET remain unaffected. However, the on-state drain current was 79% of its pre-stress value. Annealing at 350°C has no impact on the post-stress on-state drain current of the 12-μm VJFET. This leads us to attribute the degradation to a “burn-in” effect.

Abstract: In this work, we report the most recent reliability results of the 1200-V SiC vertical-channel JFETs (VJFETs) under reverse and forward bias of the gate-source diode at temperatures up to 200 °C. The preliminary results indicate that continuous forward bias stress of the gate-source diode at 200 °C for 112 hours produced no observable change in the forward conduction or transient or reverse blocking characteristics of the vertical-channel JFET. This preliminary result suggests that devices based on this structure, such as the enhancement-mode (normally off) SiC VJFET, may not be effected by the recombination enhanced defect creation process and the associated increase in on-resistance, related to body-diode conduction in the SiC DMOSFET and the SiC lateral-channel depletion-mode JFET. Since the vertical-channel JFET has no body diode, no degradation is possible from the reverse conduction mode of operation.

Abstract: 400V/2.5A 4H-SiC JFETs having a reduced surface field (RESURF) structure were fabricated. Measurements on the on-resistance, blocking and switching characteristics at high temperature were carried out. It was confirmed that the JFET has smaller dependence of on-resistance on temperature than a Si-MOSFET and positive temperature dependence of the breakdown voltage. It was also confirmed that the JFET has fast switching characteristics, that is, the turn-on and turn-off times are about 15 ns and 10 ns, at 200 °C as well as at 25 °C. A demonstration of a DC-DC converter using a module consisting of the JFET was carried out at a junction temperature of 200 °C. Stable continuous switching operation of the JFET at a junction temperature of 200 °C was confirmed.