Materials Science Forum Vols. 615-617

Abstract: The effects of using a graphite capping layer during implant activation anneal on the performance of 4H-SiC MOSFETs has been evaluated. Two sets of samples, one with the graphite cap and another without, with a gate oxide process consisting of a low-temperature deposited oxide followed by NO anneal at 1175°C for 2hrs were used for characterization. Various device parameters, particularly threshold voltage, subthreshold slope, field-effect mobility, inversion sheet carrier concentration and Hall mobility have been extracted for the two processes.

Abstract: We have examined the effect of oxidant in metalorganic chemical vapor deposition (MOCVD) of Al2O3 gate insulator on MOSFET electrical properties. High channel mobility of 311 cm2/Vs for Al2O3/SiC MOSFET is demonstrated when the Al2O3 gate insulator is deposited on HF-treated substrate at 190oC using triethyl-aluminum (TEA) and O2 as Al source and oxidant gas, respectively. This is much higher than that of Al2O3/SiC MOSFET when Al2O3 gate insulator was deposited with TEA and H2O at the same temperature. In addition, channel mobility at high gate electric field can be improved by using O2 as oxidant gas and effective mobility of 207 cm2/Vs is obtained at SiO2 equivalent gate electric field of 1.5 MV/cm.

Abstract: Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) were fabricated on p-type epitaxial 4H-SiC substrates with different surface conditions and these electrical characteristics were compared. The MOSFETs on Chemical Mechanical Polished substrates showed the drain current of the order of 10-12A at a gate voltage of 0 V, and the value of the drain current increased with increasing the surface roughness of substrates. With decreasing the surface roughness of substrates, the values of the threshold voltage decreased and the quality of gate oxide became better.

Abstract: The effect of using different orientations of 4H-SiC substrates on the performance of 4H-SiC MOSFETs has been evaluated. Three sets of samples with (0001), (000-1) and (11-20) oriented SiC substrates were used to fabricate the MOSFETs, with a gate oxide process consisting of a low- temperature deposited oxide followed by NO anneal at 1175°C for 2hrs. Various device parameters, particularly threshold voltage, subthreshold slope, field-effect mobility, inversion sheet carrier concentration and Hall mobility have been extracted. Temperature characterization up to 225°C was also performed.

Abstract: P-channel MOSFETs have been fabricated on 4H-SiC (0001) face as well as on 4H-SiC (03-38) and (11-20) faces. The gate oxides were formed by thermal oxidation in dry N2O ambient, which is widely accepted to improve the performance of n-channel SiC MOSFETs. The p-channel SiC MOSFETs with N2O-grown oxides on 4H-SiC (0001), (03-38), and (11-20) faces show a channel mobility of 7 cm2/Vs, 11 cm2/Vs, and 17 cm2/Vs, respectively. From the quasi-static C-V curves measured by using gate-controlled diodes, the interface state density was calculated by an original method. The interface state density was the lowest at the SiO2/4H-SiC (03-38) interface (about 1x1012 cm-2eV-1 at EV + 0.2 eV). The authors have applied deposited oxides to the 4H-SiC p-channel MOSFETs. The (0001), (03-38), and (11-20) MOSFETs with deposited oxides exhibit a channel mobility of 10 cm2/Vs, 13 cm2/Vs, and 17 cm2/Vs, respectively. The deposited oxides are one of effective approaches to improve both n-channel and p-channel 4H-SiC MOS devices.

Abstract: Ab initio calculations were carried out to study the origin of the trap at the SiO2/SiC (MOS: Metal-Oxide-Semiconductor) interface with the three different faces of the substrate, (0001), (000-1), and (11-20). In a previous report we experimentally discovered that the (11-20) face is suitable for high channel mobility. The calculation in this report showed that the MOS interface achieved the intermediate states due to distortion and thus acted like an interface trap. The interface trap density of the MOS interface on the (11-20) face substrate was smaller than those on the other faces. The interface trap densities were 2.14, 3.36, and 1.40 in units of 1015 cm-2 for the above listed substrate orientations, respectively. For clarity, the channel mobility was compared experimentally to reveal that it realized a larger value for the (11-20) substrate than the other two faces. From our results, we concluded that (11-20) face substrate was more suitable for high power device applications than the (0001) face or (000-1) face substrates.

Abstract: The mobility of electrons in the inversion layer of 4H-Silicon Carbide (SiC) MOSFETs is lower than the ideal value due to the various scattering mechanisms that takes place at the surface. These scattering mechanisms are strong function of both the interface-trapped charge density and inversion-layer electron density. In this work, we develop a quasi-charge-sheet model to quantify coulomb scattering due to interface trapped-charge in SiC MOSFET inversion layers and calculate the inversion layer electron mobility.

Abstract: Silicon Carbide (SiC) based metal oxide semiconductor field effect transistors (MOSFETs) were fabricated and characterized using gated hall measurements with different p-type substrate doping concentration (7.2X1016cm-3 and 2X1017 cm-3). An interface trap state density of 5X1013 cm-2eV-1 was observed nearly 0.1 eV above the conduction band edge leading to the conclusion that these states are present in the silicon dioxide rather than the interface. The Hall mobility of the MOSFETs decreased from 26.5 to 20 cm2/Vs as the doping was increased from 7.2X1016 to 2X1017cm-3. The decrease in mobility is primarily due to an increase in the surface electric field that causes an increase in surface roughness scattering. The inversion layer mobility when plotted as a function of average surface electric field is not independent of doping concentration as is the case in silicon MOSFETs because the dominant scattering mechanism is not phonon scattering.

Abstract: We build upon our previous work on 4H SiC lateral MOSFETs to present physics based numerical modeling and characterization of a 4H-SiC DMOSFET operating in ON state. Comparison of simulated ON state characteristics to experiment shows that surface roughness scattering dominates at the operating bias of VGS=15V, whereas interface trap density contributes to reducing the inversion charge in the channel and thereby increasing the ON resistance. OFF state performance of the DMOSFET was modeled by considering impact ionization in the device. Excellent leakage characteristics were observed with the device blocking 2kV drain voltage. Impact ionization related breakdown was observed at 2048V drain bias.

Abstract: Although recent fast I-V measurements and subthreshold analysis reveal that the threshold-voltage instability due to low-field bias stressing at room temperature is greater than previously reported when calculated using slower, standard measurements by a parameter analyzer—a result that is consistent with electrons directly tunneling into and out of near interfacial oxide traps, this effect will not prevent the use of power SiC DMOSFET switches in power converter applications if certain precautions are followed. Namely, if the threshold voltage is set high enough so that a negative shift in threshold voltage will not increase the leakage current in the off-state, then the primary effect will be to increase the on-state resistance by decreasing the effective gate voltage. The instability due to ON-state stressing is greater than that for bias stressing alone, but not significantly. For a well behaved device, a 1-hour ON-state stress will result in about a 7 percent increase in conduction losses, which is manageable for power converter applications.