Materials Science Forum Vols. 615-617

Abstract: After the successful introduction of silicon carbide Schottky-Barrier diodes in 2001, next commercial devices will be switching components. The development focus is targeted to MOSFETs and VJFETs. Regarding VJFETs, a promising device was presented several years ago and tested successfully in several applications. Since the unconventional device structure does not allow the use of classical JFET models, a new electro-thermal model was developed, taking into account the features of the design as well as the targeted enlarged range of operating temperatures.

Abstract: Buried gate static induction transistors (BGSITs) were fabricated on commercial 4H-SiC wafer with 20 m thick n-type epilayer having a net donor density of 0.71015 cm-3. Buried gate regions were formed by the selective implantation of high energy (up to 2 MeV) aluminium performed at 600 °C. Nitrogen was implanted at temperature of 400 °C to form a heavily doped blanket source region. Post-implantation annealing was carried out at the atmospheric pressure in argon using a graphite capping layer. Fabricated normally-on devices with source contact diameter of 0.2 mm were tested at temperatures up to 500 °C and current densities up to 270 A/cm2. The specific on-resistance of a completely open 4H-SiC BGSIT was 34 mcm2 and showed a thermally activated behaviour at temperatures up to 500 °C.

Abstract: Short-circuit capabilities of silicon carbide static induction transistors with the buried gate structures (BGSITs) have been measured for the first time, and have been followed by 2D device simulations. The short-circuit operation of the normally-on type BGSITs is characterized by an abrupt decrease in the output current through a high peak in the initial phase of the short-circuit period, which is distinguished from that of the conventional IGBTs and power MOSFETs. This operation is caused by the inherent operation of the SITs including the non-saturating current-voltage characteristics with the unipolar operation. Decreasing the channel width adequately is a useful method to increase the short-circuit capability.

Abstract: In this paper, we present the effects of MOS channel processing on the threshold voltage and the MOS field effect mobility of 4H-SiC MOSFETs. By increasing the p-well doping concentration by two orders of magnitude, the threshold voltage could be shifted positive from 0V to 5 V when a thermal oxide layer with NO post oxidation anneal was used as the gate dielectric layer. However, a severe degradation of MOS field effect mobility, decreasing from 37 cm2/Vs to 5 cm2/Vs, was also observed. Using a different processing technique, which uses a deposited oxide layer with an NO anneal, a threshold voltage of 7.5 V and a MOS field effect mobility of 15 cm2/Vs could be achieved. A 10 kV, 1 A power DMOSFET was demonstrated with this technique. A DMOSFET turn-off voltage of 5.25 V was measured at room temperature, which shifted to 3.0 V at 250oC, providing acceptable noise margins throughout the operating temperature range.

Abstract: Large area (8 mm x 7 mm) 1200 V 4H-SiC DMOSFETs with a specific on-resistance as low as 9 m•cm2 (at VGS = 20 V) able to conduct 60 A at a power dissipation of 200 W/cm2 are presented. On-resistance is fairly stable with temperature, increasing from 11.5 m•cm2 (at VGS = 15 V) at 25°C to 14 m•cm2 at 150°C. The DMOSFETs exhibit avalanche breakdown at 1600 V with the gate shorted to the source, although sub-breakdown leakage currents up to 50 A are observed at 1200 V and 200°C due to the threshold voltage lowering with temperature. When switched with a clamped inductive load circuit from 65 A conducting to 750 V blocking, the turn-on and turn-off energies at 150°C were less than 4.5 mJ.

Abstract: 4H-SiC (0001) MOSFETs with a three-dimensional gate structure, which has a top channel on the (0001) face and side-wall channels on the {11-20} face have been fabricated. The three-dimensional gate structures with a 1-5 m width and 0.8 m height have been formed by reactive ion etching, and the gate oxide has been deposited by plasma-enhanced chemical vapor deposition and then annealed in N2O ambient at 1300°C. The fabricated MOSFETs have exhibited superior characteristics: ION / IOFF, the subthreshold swing and VTH are 1010, 250 mV/decade and 3.5 V, respectively. The drain current normalized by the gate width is increasing with decreasing the gate width. The normalized drain current of a 1 m-wide MOSFET is ten times higher than that of a conventional planar MOSFET.

Abstract: SiC lateral double RESURF MOSFETs have been fabricated on the 4H-SiC (000-1)C face. By utilizing the C face, the channel resistance can be reduced because the C-face MOSFETs show higher channel mobility than the Si-face MOSFETs. In addition, by employing the double RESURF structure, the drift resistance is decreased and the breakdown voltage is increased with increasing the RESURF doses. The fabricated RESURF MOSFETs on the 4H-SiC (000-1)C face have demonstrated a low on-resistance of 40 mΩcm2 at an oxide field of 3 MV/cm and a breakdown voltage of 1580 V at zero gate bias. The figure-of-merit of the MOSFET is 62 MW/cm2, which is more than 10 times better than the conventional “Si limit” and the highest value among any lateral MOSFETs to date.

Abstract: The electrical characteristics of MOSFETs fabricated on 4H-SiC with a process based on N implantation in the channel region before the growth of the gate oxide are reported as a function of the N concentration at the SiO2/SiC interface up to 6  1019 cm-3. The field effect mobility improves with increasing N concentration. At room temperature values change from 4 cm2/Vs for the not implanted sample up to 42 cm2/Vs for the sample with the highest N concentration. Furthermore, the field effect mobility increases with temperature and presents values above 60 cm2/Vs at 200 °C. The MOSFETs with the better electrical characteristics (higher mobility, lower threshold voltage, lower subthreshold swing) were fabricated by a low thermal budget oxidation process, thank to the use of a high N implantation dose able to produce an amorphous SiC surface layer. A strong correlation among the increasing of the N concentration at the SiO2/SiC interface, the reduction of the interface state density located near the conduction band and the improvement of the MOSFETs performance was obtained.

Abstract: Conventional MOSFETs and Hall-bar MOSFETs are fabricated side by side by over-oxidation of N-implanted or N-/Al-coimplanted 4H-SiC layers. It is demonstrated that the N-/Al-coimplanted MOSFETs possess a positive threshold voltage at room temperature and reach high values of the channel mobility. The effective electron mobility and Hall mobility in Hall-bar MOSFETs are 31 cm2/Vs and 150 cm2/Vs, respectively, indicating a high density of interface traps in spite of the excellent high mobility values.

Abstract: In order to improve Silicon Carbide MOSFET device performance, it is important to minimize the on-state losses by improving the effective channel mobility, which can be done by decreasing interfacial charge consisting of interface traps, fixed charge, and oxide traps, which degrade mobility due to Coulombic scattering. This paper considers a method for distinguishing between oxide traps and fixed charge, and discusses how this charge has varied with processing over the last several years. Our results show that, over the period of study, NF has trended downward. Also, the number of switching oxide traps, which gives a lower bound for Not, appears to have decreased considerably. The trends for improvement in NF and ΔNot are promising, but our data suggests that NF and Not remain much too high and need to be reduced further to realize significant gains in SiC MOSFET performance.