Materials Science Forum Vols. 600-603

Abstract: Forward voltage of SiC pin diodes is evaluated by device simulation, where a p-type contact is described by Schottky barrier to a p-type surface region. The contact resistance is calculated from the comparison to I-V characteristic of Schottky structure to a p-SiC layer with a sufficiently low Schottky barrier height. Even in the relatively low contact resistance rc of 10-4 Wcm2, non-ohmic current component is observed in Schottky structure to p-SiC and the increase of forward voltage of pin diodes is fairly small. Forward voltage of pin diodes increases in the pin diodes with contact resistance rc over 10-4 Wcm2. The same behavior is also observed irrespective of a time constant of carriers, and doping concentration and thickness of a drift layer.

Abstract: Transient currents in 6H-SiC n+p diodes and those in Si PIN diodes are compared, and the carrier dynamic response to a heavy ion collision is analyzed using Technology Computer Aided Design (TCAD). In case of 6H-SiC n+p diodes, it is found that the contribution of the ambipolar-diffusion current to total transient current is extremely weak compared to that in Si PIN diodes, since plasma disruption is accelerated by the Auger recombination process in the former.

Abstract: 6H-SiC n+p diodes fabricated on a p-type epitaxial layer were irradiated with 1MeV-electrons at fluences up to 6×1016 cm-2 to clarify their radiation tolerance. Charge Collection Efficiencies (CCEs) were evaluated from the Transient Ion Beam Induced Current (TIBIC) using Oxygen (O) ions. The CCE of 93 % was obtained for non-electron-irradiated diodes, and no significant change in CCE was observed for diodes irradiated with electrons at fluences below 1×1015 cm-2. The degradation of CCE was observed after irradiation at fluences above 5×1015 cm-2.

Abstract: High-voltage normally-on VJFETs of 0.19 cm2 and 0.096 cm2 areas were manufactured in seven photolithographic levels with no epitaxial regrowth and a single ion implantation event. A self aligned guard ring structure provided edge termination. At a gate bias of -36 V the 0.096 cm2 VJFET blocks 1980 V, which corresponds to 91% of the 12 μm drift layer’s avalanche breakdown voltage limit. It outputs 25 A at a forward drain voltage drop of 2 V (368 A/cm2, 735 W/cm2) and a gate current of 4 mA. The specific on-resistance is 5.4 mΩ cm2. The 0.19 cm2 VJFET blocks 1200 V at a gate bias of -26 V. It outputs 54 A at a forward drain voltage drop of 2 V (378 A/cm2, 755 W/cm2) and a gate current of 12 mA, with a specific on-resistance of 5.6 mΩ cm2. The VJFETs demonstrated low gate-to-source leakage currents with sharp onsets of avalanche breakdown.

Abstract: In this work we report the most recent high-temperature long-term reliability results of the 600 V/14 A, 4H-SiC vertical-channel junction field-effect transistors (VJFETs). Two groups (A and B) devices were subjected to different thermal and electrical stresses. One device (Group A) reached 12,000 hours of continuous switching without a single failure. Four devices in Group A were thermally stressed at 250 °C over 4,670 hours in air, for which standard deviation of the specific on-resistance (RONSP) in linear region at gate bias (VGS) of 3 V were < 4.1% throughout the entire duration time. The off-state characteristics were evaluated by high temperature reverse bias (HTRB) tests. Three devices (Group A) were biased at 50% rated BVDS at 250 °C for 2,278 hours. A higher reverse bias at 80 % rated BVDS was then applied to 14 devices (group B) at 200 °C for 1,000 hours. Variations of the leakage current were negligible throughout the entire HTRB test for all tested devices.

Abstract: In this work we have demonstrated the high-temperature operations of 600 V/50 A 4HSiC vertical-channel junction field-effect transistors (VJFETs) with an active area of 3 mm2. Specific-on resistance (RONSP) in the linear region of a single die is less than 2.6 mW.cm2 while the drain-source current is over 50 A under a gate bias (VGS) of 3 V. A reverse blocking gain of 54 is obtained at gate bias ranging from -13 V to -23 V and drain-source leakage current (IRDS) of 200 μA. To demonstrate the use of SiC VJFETs for high-power applications, eight 3 mm2 SiC VJFETs are bonded in a high current 600-V module. RONSP in the linear region of these eight-paralleled SiC VJFETs is 2.8 mW.cm2 at room temperature and increased to 5.35 mW.cm2 at an ambient temperature of 175 °C in air, corresponding to a shift of 0.61%/°C from room temperature to 175 °C. Meanwhile, the forward current is over 360 A at room temperature and reduces to 188 A at 175 °C at drain-source bias (VDS) of 5.25 V and VGS of 3 V.

Abstract: We developed normally-off 4H-SiC vertical junction field effect transistors (JFETs) with large current density. The effect of forming an abrupt junction between the gate and the channel was simulated, and vertical JFETs were then fabricated with abrupt junctions. As a result, a large rated drain current density (500 A/cm2) and a low specific on-resistance (2.0 mWcm2) were achieved for small devices. The blocking voltage was 600 V. These results were due to a reduction of the threshold voltage by forming the abrupt junction between the gate and the channel.

Abstract: Trenched and implanted vertical JFETs (TI-VJFETs) with blocking voltages of 700 V were fabricated on commercial 4H-SiC epitaxial wafers. Vertical p+-n junctions were formed by aluminium implantation in sidewalls of strip-like mesa structures. Normally-on 4H-SiC TI-VJFETs had specific on-state resistance (RO-S ) of 8 mW×cm2 measured at room temperature. These devices operated reversibly at a current density of 100 A/cm2 whilst placed on a hot stage at temperature of 500 °C and without any protective atmosphere. The change of RO-S with temperature rising from 20 to 500 °C followed a power law (~ T 2.4) which is close to the temperature dependence of electron mobility in 4H-SiC.

Abstract: Static and dynamic behavior of the epitaxially grown dual gate trench 4H-SiC junction field effect transistor (JFET) is investigated. Typical on-state resistance Ron was 6 – 10mΩcm2 at VGS = 2.5V and the breakdown voltage between the range of 1.5 – 1.8kV was realized at VGS = −5V for normally-off like JFETs. It was found that the turn-on energy delivers the biggest part of the switching losses. The dependence of switching losses from gate resistor is nearly linear, suggesting that changing the gate resistor, a way similar to Si-IGBT technology, can easily control di/dt and dv/dt. Turn-on losses at 200°C are lower compared to those at 25°C, which indicates the influence of the high internal p-type gate layer resistance. Inductive switching numerical analysis suggested the strong influence of channel doping conditions on the turn-on switching performance. The fast switching normally-off JFET devices require heavily doped narrow JFET channel design.

Abstract: We have succeeded to fabricate SiC buried gate static induction transistors (BGSITs) with the breakdown voltage VBR of 1270 V at the gate voltage VGS of –12 V and the specific on-resistance RonS of 1.21 mΩ·cm2 at VGS = 2.5 V. The turn-off behaviors of BGSITs strongly depend on the source length WS, which is the distance between the gate electrodes. The rise time tr of BGSIT for WS = 1,070 μm is 395 nsec, while that for WS = 210 μm is 70nsec. From the 3D computer simulations, we confirmed that the difference in turn-off behavior came from the time delay in potential barrier formation in channel region because of high p+ gate resistivity. The turn-off behaviors also depend on the operation temperature, especially for long WS. On the other hand, the turn-on behaviors hardly depend on the WS and temperature.