Materials Science Forum Vols. 600-603

Abstract: In order for SiC-MOSFET to be practical in various power electronics applications, low specific on-resistance Ron,sp, high breakdown voltage and “normally-off” characteristics have to be fulfilled even at high temperature. We fabricated a SiC-MOSFET employing a submicron gate with channel length Lg of 0.5μm by a self-aligned implantation and aδ-doped epitaxial channel layer to successfully demonstrate the following features. The normally-off characteristics was confirmed from room temperature to 200°C where the therethold voltages Vth were 2.9V at room temperature and 1.6V at 200°C, respectively. The Ron,sp were 4.6mΩcm2 at room temperature and 9.2mΩcm2 at 200°C, respectively, while the breakdown voltage was greater than 1400V .

Abstract: We have investigated the techniques to improve the channel mobility of SiC MOSFETs and found that the hydrogen termination of dangling bonds at a MOS interface is very effective in improving the channel mobility, particularly that of the interface fabricated on a (11-20) face wafer. A high channel mobility of MOSFET on the (11-20) face was achieved to 244cm2/Vs by new process which can terminate dangling bonds by hydrogen. The vertical MOSFET, which is prepared using this process, has a low on-resistance of 5.7 mΩcm2 and a breakdown voltage of 1100 V. The channel resistance is estimated at 0.58 mΩcm2.

Abstract: The shout-circuit ruggedness of prototype 1.2kV SiC MOSFETs has been investigated. The short-circuit measurements were carried out at 25 °C and 125 °C with a dc bus voltage of 800 V and an on/off state gate voltage of +20/-10 V. The small difference in tfail between 25 °C and 125 °C indicates that the destructive breakdown occurs at temperatures much higher than 125 °C. The temperature at destructive breakdown estimated from the Wunsch-Bell formula is about 1400 °C. At such high temperatures, intrinsic carriers are increased markedly and generated heat leads to the destructive breakdown. tfail of all the SiC-MOSFETs studied is longer than 10 μs, meaning that the short-circuit ruggedness satisfies system requirements. These results show that the SiC-MOSFETs are promising for power electronics applications.

Abstract: This paper presents the effect of recombination-induced stacking faults on the drift based forward conduction and leakage currents of high voltage 4H-SiC power devices. To show the effects, IV characteristics of a 4H-SiC 10 kV DMOSFET and a 4H-SiC 4 kV BJT have been evaluated before and after the induction of stacking faults in the drift epilayer. For both devices, significant increases in forward voltage drops, as well as marked increases in leakage currents have been observed. The results suggest that injection of minority carriers in majority carrier devices should be avoided at all times.

Abstract: SiC vertical MOSFETs were fabricated and characterized to achieve a blocking voltage of 950 Volts and a specific on-resistance of 8.4 mW-cm2. Extrapolations of time-dependent dielectric breakdown measurements versus applied electric field indicate that the gate oxide mean-time to failure is approximately 105 hours at 250°C.

Abstract: In this paper, large area (0.18cm2) SiC DMOSFETs with 1.2 kV and 20 A rating are evaluated for power electronic switching applications. A drain-to-source voltage drop VDS of 2 V at a forward drain current of 20 A (JD = 110 A/cm2) was obtained and a specific on-resistance of 18 mΩ-cm2 was extracted at room temperature. The device on-resistance was measured up to 150°C and initially decreases with increasing temperature, but remains relatively flat over the entire temperature range, demonstrating stable device behavior. High voltage blocking of 1.2 kV between 25°C and 150°C is also demonstrated with a gate-to-source voltage VGS = 0 V. The drain leakage current under reverse bias and high temperature stress is shown to increase from 10 μA at 25°C to 27 μA at 150°C while maintaining the full blocking rating of the device. Experimental results from double-pulse clamped inductive load tests are presented demonstrating fast high voltage and high current switching capability. High voltage resistive-switching measurements on parallel connected SiC DMOSFETs were performed with VDS having rise and fall times of 49 and 74 ns respectively. Thermal camera images taken of parallel connected DMOSFET die during repetitive switching operation with VDS = 420 V, IDS = 25 A and a 40% duty cycle shows a 2°C difference in die temperature, which suggests even current sharing and temperature stable device operation.

Abstract: For the first time, large area 10 kV SiC power devices are being produced capable of yielding power modules for high-frequency megawatt power conversion. To this end, the switching performance and power dissipation of silicon carbide (SiC) n-channel IGBTs and MOSFETs are evaluated using numerical simulations software over an extended current range to determine the best device suitable for 10 kV applications. Each device is also optimized for minimal forward voltage drop in the on-state.

Abstract: We compare the on-state and switching performance of high-voltage 4H-SiC n-channel DMOSFETs and p-channel IGBTs within a three-dimensional parameter space defined by blocking voltage, switching frequency, and current density. We determine the maximum current density each device can carry at a given switching frequency, such that the total power dissipation is 300 W/cm2. The IGBT current depends strongly on lifetime in the NPT buffer layer, and only weakly on lifetime in the drift layer. The MOSFET current is essentially independent of frequency.

Abstract: Threshold voltage (Vth) was measured on 4H-SiC power DMOSFET devices as a function of temperature, gate stress, and gate stress time. Vth varied linearly with gate stress and gate stress time and inversely with temperature. This instability is explained with the trapping rate of channel electrons at or near the SiO2-SiC interface. Since the measurement scale of Vth is large in this case (it takes approx. 20 s to measure Vth), it is assumed that fast interface traps, i.e., ones closer to the interface, are already filled and do not contribute to the shift in Vth. Comparison with theoretical calculations shows the rate of carrier detrapping becomes higher with temperature and as a result the measured value of Vth approaches the theoretical value.

Abstract: This paper reports a 4H-SiC bipolar junction transistor (BJT) with a breakdown voltage (BVCEO) of 1200 V, a maximum current gain (β) of 60 and the low on-resistance (Rsp_on)of 5.2 mΩcm2. The high gain is attributed to an improved surface passivation SiO2 layer which was grown in N2O ambient in a diffusion furnace. The SiC BJTs with passivation oxide grown in N2O ambient show less emitter size dependence than reference SiC BJTs, with conventional SiO2 passivation, due to a reduced surface recombination current. SiC BJT devices with an active area of 1.8 mm × 1.8 mm showed a current gain of 53 in pulsed mode and a forward voltage drop of VCE=2V at IC=15 A (JC=460 A/cm2).