Materials Science Forum Vols. 600-603

Abstract: This paper reports a newly achieved best result on the common emitter current gain of 4H-SiC high power bipolar junction transistors (BJTs). A fabricated 1600 V – 15 A 4H-SiC power BJT with an active area of 1.7 mm2 shows a high DC current gain (b) of 70, when it conducts 9.8 A collector current at a base current of only 140 mA. The maximum AC current gain (DIC/DIB) is up to 78. This high performance BJT has an open base collector-to-emitter blocking voltage (VCEO) of over 1674 V with a leakage current of 1.6 μA, and a specific on-resistance (RSP-ON) of 5.1 mW.cm2 when it conducts 7.0 A (412 A/cm2) at a forward voltage drop of VCE = 2.1 V. A large area 4H-SiC BJT with a footprint of 4.1 mm x 4.1 mm has also shown a DC current gain over 50. These high-gain, high-voltage and high-current 4H-SiC BJTs further support a promising future for 4H-SiC BJT applications.

Abstract: 4H-SiC BJTs with a common emitter current gain (b) of 108 at 25°C have been demonstrated. The high current gain was accomplished by using a base as thin as 0.25 μm. The current gain decreases at high temperatures but is still greater than 40 at 300°C. The device demonstrates an open emitter breakdown voltage (BVCBO) of 1150 V, and an open base breakdown voltage (BVCEO) of 250 V. A low specific on-resistance of 3.6 mW-cm2 at 25°C was achieved. The BJTs have shown blocking capabilities over a wide range of operating temperatures up to 300°C.

Abstract: This paper presents a simulation study on the thermal effects in 4H-SiC NPN BJTs. Simulation results show several important effects on the BJT characteristics such as base contact locations, current gain reduction due to high level injection in the base at high current densities, and the non-uniform current distribution due to long fingers and poor contact resistance. A DC spice model with temperature effects is created. The IVs of the model are in good agreement with measurement.

Abstract: Continued improvement in silicon carbide (SiC) material processing has allowed development of efficient high temperature devices which are uniquely suited to power electronics circuit designs. The 4H-SiC structure has several intrinsic characteristics that facilitate optimal speed and power handling during high temperature device operation. These characteristics include wide bandgap (3.2 eV), high dielectric breakdown (3.5 MV/cm), and high thermal conductivity (4.9 W/cm-K)[1,2]. By combining these properties, SiC bipolar junction transistors (BJTs) can achieve fast, low impedance switching at high voltages (1.2 kV). New generation devices are being developed with increased current handling capability, as well as improved forward voltage characteristics. The device considered here, along with its on-state DC characteristic, is shown in figure 1. The BJTs are approximately 5mm by 5mm, and are nominally rated for a maximum Ice of 50A. Measurements on the Tektronix 371B curve-tracer indicate current gains over 60 at 25 oC and roughly 40 at 150 oC. These results were obtained at collector currents up to 20A. The base current for BJTs is typically 300 to 800 mA, depending on device temperature and the maximum device current required. In order to meet current handling requirements of up to 80A, as required for power conversion in modern military systems such as the hybrid-electric vehicle (HEV), it is necessary to configure these devices in parallel with minimal external cooling. The resulting switching circuits must therefore be validated for operation at high temperatures (package temperatures of 90 oC, and junction temperatures to 150 oC). Validation includes characterization of the devices in clamped inductive circuits with devices configured both alone and in parallel over time. Figure 4 shows measurement waveforms obtained during continuous clamped inductive switching. The primary focus of this work is to establish the overall performance and reliability of these newer generation SiC BJTs in power conversion circuits. Failure analysis and critical performance issues, such as current sharing, energy loss, and total reverse recovery charge are addressed. The initial results of the experiments indicate that these SiC switches have the potential to perform reliably in high temperature power conversion.

Abstract: To determine the maximum allowed power dissipation in a power transistor, it is important to determine the relationship between junction temperature and power dissipation. This work presents a new method for measuring the junction temperature in a SiC bipolar junction transistor (BJT) that is self-heated during DC forward conduction. The method also enables extraction of the thermal resistance between junction and ambient by measurements of the junction temperature as function of DC power dissipation. The basic principle of the method is to determine the temperature dependent I-V characteristics of the transistor under pulsed conditions with negligible self-heating, and compare these results with DC measurements with self-heating. Consistent results were obtained from two independent temperature measurements using the temperature dependence of the current gain, and the temperature dependence of the base-emitter I-V characteristics, respectively.

Abstract: The behavior of stacking faults with regard to Vf degradations and TEDREC phenomena for 4.5 kV SiCGT have been investigated through the use of light emission images. Stacking faults, which cause Vf degradations, are expanded when current densities are increased. A novel phenomena of Vf degradation reduction, TEDREC phenomena, was found, which can reduce degradation by increasing operating temperature. It was observed for the first time that stacking faults become inactive by elevating temperatures to more than 150 oC in spite of existing stacking faults, which is a factor that contributes to TEDREC phenomena.

Abstract: To reduce the switching power losses of SiC bipolar devices, an electron irradiation lifetime control method was investigated and was successfully applied to the development of 200kVA full SiC inverters, in which SiCGTs and SiC pn diodes irradiated electrons were used at the condition required to minimize inverter power loss.

Abstract: For the first time, high power 4H-SiC n-IGBTs have been demonstrated with 13 kV blocking and a low Rdiff,on of 22 mWcm2 which surpasses the 4H-SiC material limit for unipolar devices. Normally-off operation and >10 kV blocking is maintained up to 200oC base plate temperature. The on-state resistance has a slight positive temperature coefficient which makes the n-IGBT attractive for parallel configurations. MOS characterization reveals a low net positive fixed charge density in the oxide and a low interface trap density near the conduction band which produces a 3 V threshold and a peak channel mobility of 18 cm2/Vs in the lateral MOSFET test structure. Finally, encouraging device yields of 64% in the on-state and 27% in the blocking indicate that the 4H-SiC n-IGBT may eventually become a viable power device technology.

Abstract: DC characteristics of 4H-SiC p-channel IGBTs capable of blocking -12 kV and conducting -0.4 A (-100 A/cm2) at a forward voltage of -5.2 V at 25°C are demonstrated for the first time. A record low differential on-resistance of 14 mW×cm2 was achieved with a gate bias of -20 V indicating a strong conductivity modulation in the p-type drift region. A moderately doped current enhancement layer grown on the lightly doped drift layer effectively reduces the JFET resistance while maintains a high carrier lifetime for conductivity modulation. A hole MOS channel mobility of 12.5 cm2/V-s at -20 V of gate bias was measured with a MOS threshold voltage of -5.8 V. The blocking voltage of -12 kV was achieved by Junction Termination Extension (JTE).

Abstract: We have designed, simulated, fabricated, and characterized high-voltage 4H-SiC p-channel DMOS-IGBTs on 20 kV blocking layers for use as the next generation of power switching devices. These p-IGBTs exhibit significant conductivity modulation in the drift layer. The maximum currents of the experimental p-channel IGBTs are 1.2x and 2.1x higher than the ideal 20 kV n-channel DMOSFETs at room temperature and 175°C, respectively.