Materials Science Forum Vols. 600-603

Abstract: The operation of metal-oxide-semiconductor (MOS) devices based on the semiconductor SiC in high temperature environments above 300 °C requires an understanding of the physical processes in these capacitor structures under operating conditions. In this study we have focused on the regime of inversion biasing, where the electrical characteristics of the device are dominated by minority carriers. We report on the direct observation of the high frequency inversion capacitance due to thermal generation of holes in 6H-SiC n-MOS capacitors between 450 and 600 °C by monitoring the 1MHz C-V characteristics of large area, 1000 μm diameter, capacitors in the dark. Our experimental results are consistent with a first order calculation based on the delta depletion approximation.

Abstract: We have analyzed the effect of post-oxidation nitride anneals (usually with either NO or N2O gases) on SiC MOSFETs. Two 4H:SiC wafers were identically prepared except that one wafer had a nitridation anneal after the gate oxide was formed, while the other was tested as-oxidized. We compared the two processes by making measurements on lateral MOSFETs and MOS capacitors using ID-VGS, C-V, and charge pumping. There was no change in either flatband voltage or interface trap density near the valence band, suggesting that the net fixed charge remained constant (within a few 1011cm-2). However, there was a large shift in the threshold voltage which, when combined with the C-V results, indicates a strong reduction of interface traps near the conduction band of roughly 6.0x1012cm-2 by using the nitridation process. The charge pumping measurements also showed a strong reduction of interface traps. Charge pumping measured a trapping density of 2.5x1012cm-2 for the as-oxidized samples and 5.3x1011cm-2 for the nitrided samples. The frequency-dependence of the charge pumping signal also indicates a spatial distribution of traps, with volumetric trap densities of roughly 1.3x1019cm-3 over 25Å on as-oxidized and 3.8x1018cm-3 over 19Å for nitrided.

Abstract: This paper describes the influence of the geometric component in the charge-pumping measurement of 4H-SiC MOSFETs. Charge-pumping measurements were conducted on 4H-SiC MOSFETs with and without NO annealing. Charge-pumping measurements with different pulse-fall times revealed that the geometric component exists in 4H-SiC MOSFETs and is especially large in the unannealed MOSFETs. A sufficiently long fall-time is needed to minimize its effect, which is expected to be 1–10 μs for 4H-SiC MOSFETs with a gate length of 10 μm.

Abstract: The effect of incorporation of cesium with implantation on the electrical characteristics of SiO2/4H-SiC interface has been evaluated using MOS capacitors. With a cesium dosage of 1012 and 3x1012 cm-2 on deposited oxide re-oxidized in steam, effective oxide charge densities of - 1.4x1012 and -7.5x1011 cm-2 respectively were extracted and a cesium implant activation percentage of 33% was estimated from flatband voltage shift. Also, corresponding interfacial state densities of 2.5x1013 and 1.8x1013 cm-2-eV-1 near the conduction band edge were extracted from High-Low frequency C-V technique, showing a decreasing Dit with increasing Cs dosage.

Abstract: This study is focused on characterization of deep energy-level interface traps formed during sodium enhanced oxidation of n-type Si face 4H-SiC. The traps are located 0.9 eV below the SiC conduction band edge as revealed by deep level transient spectroscopy. Furthermore these traps are passivated using post-metallization anneal at 400°C in forming gas ambient.

Abstract: In this study we report interface and carrier transport behaviour in Al/HfO2/SiO2/SiC MIS structure. The density of the interface states (Dit) and the oxide trapped charges (Not) are found to be ~7 x 1011 eV-1cm-2 @ Ec-Et = 0.2 eV, and ~ 4.8 x 1011 cm-2. The temperature dependencies on gate current density are explored to study the different charge transport mechanisms through the HfO2-based dielectric stack on 4H-SiC. In the low voltage region, the conduction mechanism is controlled by a space charge limited or electronic hopping conduction process. Beyond this region (1.25 MV/cm 2.5 MV/cm), and at higher temperatures Schottky emission (SE) fits the data very well. The barrier height is found to be ~1.5 eV, which is higher than the value for just HfO2 on SiC

Abstract: Aluminium oxynitride (AlON) films of variable composition were grown by reactive sputter deposition in a N2/O2 ambient at room temperature and studied for device passivation. The films were deposited on Si and 4H-SiC substrates as well as on SiC PiN diodes. The AlON/SiO2/SiC stack provided superior interface properties compared to the AlON/SiC structure. Samples with 8% oxygen content, in the AlON film, and subjected to a UV exposure prior to deposition, exhibited the smallest net positive interface charge. A large net negative interface charge was observed for samples with 10% oxygen content and for the samples with 8% oxygen content and subjected to a RCA1 surface clean, prior to deposition. Diodes passivated with AlON films demonstrated reduced leakage current compared to as-processed diodes.

Abstract: The interface properties of TiO2/SiO2/SiC metal-insulator-semiconductor (MIS) capacitors were investigated by C-V and G-V measurements over a range of frequencies between 10 kHz and 1 MHz from room temperature up to 500°C. Ledges from multiple traps were observed during high frequency (1 MHz) sweeps from inversion to accumulation during measurements at elevated temperatures. The high measuring temperature resulted in the annealing of the sample, where the existence of trap ledges was observed to be temperature dependent. For n-type substrate negative Qf causes the shift of the C-V curve to more negative gate bias with respect to the ideal C-V curve. These fixed oxide charge is substantially reduced after post metallization annealing (PMA). We report the flat band voltage, detail in reducing fixed oxide charge and temperature dependence of density of interface traps before and after annealing of TiO2 high-κ gate dielectric stacks on a 4H-SiC based device.

Abstract: In this work, the correlation between thermal oxide breakdown and dislocations in n-type 4H-SiC epitaxial wafers has been investigated. Thermal oxide was grown by oxidation in N2O at 1250°C followed by annealing in NO atmosphere. The electron beam induced current (EBIC) technique was employed to find correlations between the electrically active defects in epitaxial layers and regions where the oxide breakdowns occurred. The test measurements of leakage currents in MOS devices were performed in order to correlate the leakage currents with number of defects in the epi-layer detected by EBIC technique.