Materials Science Forum Vols. 615-617

Abstract: The so-called “growth” of graphene was performed using a horizontal chemical vapor deposition (CVD) hot-wall reactor. In-situ etching in the mixture (H2-C3H8) was performed prior to growth at 1600oC temperature under 100 mbar. Systematic studies of the influence of the decomposition temperature and time, substrates roughness, etching of the substrates, heating rate, SiC dezorientation and other process parameters on the graphene thickness and quality have been conducted. Morphology and atomic scale structure of graphene was examined by Scanning Tunnelling Microscopy (STM), Transmission Electron Microscopy (TEM) and Raman scattering methods.

Abstract: We report a comparative investigation of few layers graphene grown on 6H, 4H and 3C-SiC substrates. We show that the size of the graphitic domains depends more on the <0001> SiC surface orientation than the polytypism.

Abstract: Transmission Electron Microscopy (TEM) investigations of graphene layers on Si terminated 4H-SiC(0001) are presented. The graphene layers have been grown in a standard method using decomposition of silicon carbide. Two kind of graphene layers have been investigated: 1) grown on substrates with on-axis orientation, 2) grown on substrates with 4° and 8° off-axis orientation in respect of c-axis of SiC. In the case of 0° orientation the high resolution TEM micrographs revealed that a thin layer graphene is present: 1-3 monolayers were obtained. It was found that the first carbon layer was about 2Å from the SiC surface. This result indicates that a strong covalent bonds between carbon layer and silicon atoms on the SiC surface exist. The subsequent graphene layers have been found spaced by 3.4 Å - similar as in the graphite. That indicates a weak van der Waals bonding between subsequent carbon layers. In the case of 4° and 8° off-axis orientation a thicker layer of about 5-6 monolayers of graphene were obtained. Relative spacings of graphene layers were the same as in the case of on-axis orientation.

Abstract: Graphene layers were created on both C and Si faces of semi-insulating, on-axis, 4H- and 6H-SiC substrates. The process was performed under high vacuum (<10-4 mbar) in a commercial chemical vapor deposition SiC reactor. A method for H2 etching the on-axis substrates was developed to produce surface steps with heights of 0.5 nm on the Si-face and 1.0 to 1.5 nm on the C-face for each polytype. A process was developed to form graphene on the substrates immediately after H2 etching and Raman spectroscopy of these samples confirmed the formation of graphene. The morphology of the graphene is described. For both faces, the underlying substrate morphology was significantly modified during graphene formation; surface steps were up to 15 nm high and the uni-form step morphology was sometimes lost. Mobilities and sheet carrier concentrations derived from Hall Effect measurements on large area (16 mm square) and small area (2 and 10 m square) samples are presented and shown to compare favorably to recent reports.

Abstract: We report an investigation of few layers graphene exfoliated on SiC. Using AFM and Raman spectroscopy, we find that the graphene thickness determined from the normalized intensity of Raman lines significantly depart from the one obtained using XPS.

Abstract: The structural and electronic properties of epitaxial graphene on SiC(0001) are investigated by low energy electron diffraction (LEED) and angle resolved ultraviolet photoelectron spectroscopy (ARUPS). Fingerprints in the spot intensity spectra in LEED allow for the exact determination of the number of layers for the first three graphene layers after being correlated with the electronic bandstructure obtained from ARUPS using He II excitation. Our analysis includes the consideration of samples with different doping levels. A possible influence of the polytype 4H- or 6H-SiC is discussed. LEED by itself turns out to be an easy and practical method for the thickness analysis of epitaxial graphene on SiC(0001).

Abstract: This paper reports the investigation of epitaxial graphene growth on 4H-SiC substrates. Growth has been performed under ultra high vacuum (UHV) conditions at temperatures ranging from 1150 to 1250°C, and the formation of the graphene layer has been monitored using X-ray photoelectron spectroscopy (XPS). A gradient of 100°C in temperature was introduced across the sample in order to grow a wide range of thicknesses along the sample. Atomic force microscopy (AFM) of the surface shows that the epitaxial graphene layer follows the topography of the bulk material and introduces very little surface roughness. This paper also reports the electrical characterisation of the graphene layers.

Abstract: Carbon is able to crystallise in different allotrope modifications. They mainly differ in the dominating bindings formed in dependence on the hybridization sp, sp2 and sp3 of the carbon atoms. The present work demonstrates the formation of two different forms of car¬bon allotropes by heating both polar surfaces of on axis 6H-SiC(0001) and 6H-SiC(000 ) crystals to temperatures above 1600°C. In consequence of the structural evolution graphite-like (sp2-hybridised) and carbine-like (sp-hybridised) allotropic carbon modifications were obtained.

Abstract: Vertically aligned multiwall carbon nanotubes were directly grown by means of thermal Chemical Vapor Deposition onto epitaxial and bulk double side polished 4H-SiC substrates. Their structure and morphology have been examined through Field Emission Scanning Electron Microscopy and Raman spectroscopy. The results have been compared with CNTs carpets grown in the same conditions on Si substrates. Preliminary analysis of their electrical properties has been performed using the four-point probe technique in order to evaluate their resistivity.

Abstract: In this work, SiC nanowire (NW) FETs are prepared and their electrical measurements are presented. From the samples fabricated on the same substrate, various I-Vs shapes are obtained (linear, non linear symmetric, and asymmetric). With the assistance of simulation, we show that this is a result of different values of Schottky Barrier Heights (SBH) at Source (S) / Drain (D) contacts of FETs. An origin for this might be a non uniformity in annealing, NW doping level and high interface traps density (that pins the Fermi level) as well as the high sensitivity of the metal-NW contacts to local surface contaminations.